bbracker
78e513160e
put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests
2021-07-19 16:19:24 -04:00
bbracker
d603f4ea57
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:42:26 -04:00
bbracker
009e9d97bf
adapt testbench to removal of ReadDataWEn signal
2021-07-19 15:42:14 -04:00
bbracker
02de6014b2
adapt testbench to removal of signal
2021-07-19 15:41:50 -04:00
bbracker
76be84fa92
whoops MTIMECMP is always 64 bits
2021-07-19 15:40:53 -04:00
Abe
55391a8ef6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:20:38 -04:00
kipmacsaigoren
cbbfc2d3fc
removed Wally test framwork include statement
2021-07-19 19:15:11 +00:00
bbracker
fb6e618b1c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 15:13:14 -04:00
bbracker
77b690faf0
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
c1c564d54c
added changes to priority encoders from synthesis branch (correctly this time I hope)
2021-07-19 15:06:14 -04:00
Ross Thompson
5edd513f8c
Furture simplification of the dcache ReadDataW update.
2021-07-19 12:46:31 -05:00
Ross Thompson
5754b5f25f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-19 12:32:35 -05:00
Ross Thompson
2ee97efb9c
Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.
2021-07-19 12:32:16 -05:00
bbracker
8cbd83e804
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 13:21:04 -04:00
bbracker
2702064dda
change buildroot expectations to match reality
2021-07-19 13:20:53 -04:00
Kip Macsai-Goren
0c8a179c0b
rename page table levels
2021-07-19 13:00:59 -04:00
Kip Macsai-Goren
6f5e1b9d01
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 13:00:25 -04:00
Ross Thompson
6ccbdc372d
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
bbracker
986b7a8252
change sram1rw to have a small delay so that we don't have signals changing on clock edges
2021-07-19 11:30:07 -04:00
Kip Macsai-Goren
f9fdd456bd
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 10:56:48 -04:00
Kip Macsai-Goren
9c7158bfc9
Revert "added priority circuit to attempt to remove delay due to rippling in pmpadrdec"
...
This reverts commit 9461fd9fbd51e17a416a7df6982379fbfa6b0974.
2021-07-19 10:46:17 -04:00
David Harris
1b55f584c7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 10:34:18 -04:00
Kip Macsai-Goren
704444a3c5
added priority circuit to attempt to remove delay due to rippling in pmpadrdec
2021-07-19 10:34:17 -04:00
James Stine
62b4ef6953
delete sbtm_a4 and sbtm_a5 as they are not needed
2021-07-19 08:06:00 -05:00
James Stine
892bc68918
remove sbtm3.sv - not needed
2021-07-19 08:00:53 -05:00
James Stine
55f2720f89
update part I on sbtm change
2021-07-19 07:59:27 -05:00
David Harris
0c41b8102d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-19 00:25:06 -04:00
Abe
9991265beb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-18 23:09:57 -04:00
Katherine Parry
8d101548f1
FDIV and FSQRT passes when simulating in modelsim
2021-07-18 23:00:04 -04:00
bbracker
f209cf0100
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-18 21:50:05 -04:00
bbracker
64a81941ff
change memread testvectors to not left-shift bytes and half-words
2021-07-18 21:49:53 -04:00
David Harris
4729a72167
Updated FMA1 with parameterized size
2021-07-18 20:40:49 -04:00
James E. Stine
26f146242e
temp fpdivsqrt
2021-07-18 20:04:18 -04:00
bbracker
f4f3ef0307
linux testbench progress
2021-07-18 18:47:40 -04:00
David Harris
398e9583e9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-18 17:36:29 -04:00
David Harris
f22b6e7397
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
Katherine Parry
3527620c0b
fdivsqrt inegrated, but not completley working
2021-07-18 14:03:37 -04:00
David Harris
e31d2ef9f5
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
David Harris
e962324d00
LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall
2021-07-18 03:51:30 -04:00
David Harris
40c5d3ced7
HPTW: Simpliifieid PRegEn
2021-07-18 03:35:38 -04:00
David Harris
a5a7be3e03
Removed EndWalk signal and simplified TLBMissReg
2021-07-18 03:26:43 -04:00
Ross Thompson
a0017e39e2
Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
2021-07-17 21:02:24 -05:00
Ross Thompson
d0ed6e250a
Fixed LRSC in 64bit version. 32bit version is broken.
2021-07-17 20:58:49 -05:00
David Harris
3be88117c5
added lrsc.sv
2021-07-17 21:15:08 -04:00
David Harris
c29a2ff8df
Started atomics
2021-07-17 21:11:41 -04:00
David Harris
3783b5dc00
moved subwordread to lsu
2021-07-17 20:37:20 -04:00
David Harris
84f579038c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-17 20:01:23 -04:00
David Harris
d441d4270c
LSU cleanup
2021-07-17 20:01:03 -04:00
David Harris
f21582906f
Pushing HPTWPAdrM flop into LSUArb
2021-07-17 19:39:18 -04:00
David Harris
989bb7c01b
Simplified VPN case statement
2021-07-17 19:34:01 -04:00
