David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Kevin
98420cb988
dot stars conversions on the rest of the testbenches
2021-12-12 17:53:26 -08:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Ross Thompson
7497422667
Changed several things.
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Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Ross Thompson
32f0b97cd3
Updated uncore to use sdc.
...
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
Ross Thompson
d11136c406
Fixed bug with the external memory region selection.
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Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
Ross Thompson
fca9b9e593
Movied tristate to test bench level.
2021-09-30 11:27:42 -05:00
Ross Thompson
cefbcd1b0c
Partially sd card read on fpga.
2021-09-30 11:23:09 -05:00
Ross Thompson
7ca801113e
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
Ross Thompson
7d749b201b
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
c917f14b6b
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
69674f272a
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
44196af61a
Have program which checks for sdc init and issues read, but read done is
...
not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
4f7bc1be48
Added either the sdModel or constant driver for the SDC ports in all test benches.
2021-09-24 12:31:51 -05:00
Ross Thompson
296da4f437
FPGA test bench and test program.
2021-09-12 20:41:54 -05:00
