Thomas Fleming
e807f5d771
Implement support for superpages
2021-04-08 02:44:59 -04:00
Thomas Fleming
f9bf2fbc01
Implement sfence.vma and fix tlb writing
2021-04-01 15:55:05 -04:00
Thomas Fleming
e3d548d452
Merge remote-tracking branch 'origin/main' into main
...
Bring icache and MMU code together
Conflicts:
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2
Complete basic page table walker
2021-03-30 22:19:27 -04:00
ushakya22
ba01d57767
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
bbracker
5327dcfcc8
instrfaults not respecting stalls bugfix
2021-03-25 00:16:26 -04:00
Shreya Sanghai
09b90557f7
PC counts branch instructions
2021-03-23 14:25:51 -04:00
Shreya Sanghai
f35d3b39c8
removed unnecesary PC registers in ifu
2021-03-18 16:31:21 -04:00
Thomas Fleming
062c4d40da
Connect tlb, pagetablewalker, and memory
2021-03-18 14:35:46 -04:00
Ross Thompson
ccaaa829ce
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac
Cleanup of the branch predictor flush and stall controls.
2021-03-12 14:57:53 -06:00
Thomas Fleming
97e9baa316
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
e48dc38869
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Ross Thompson
619bbd9d83
Merge branch 'bp' into main
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Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
d0223da2f7
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe
Install dtlb in dmem
2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5
Install tlb into ifu
2021-03-04 03:11:34 -05:00
Ross Thompson
6191fcb1af
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
0258901865
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
225102047a
Clean up bus interface code
2021-02-26 01:03:47 -05:00
David Harris
38b8cc652c
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
Ross Thompson
597dd1e7e6
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
bbe0db3ebe
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
David Harris
cc42655789
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
David Harris
842c374de9
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
33110ed636
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
