Ross Thompson
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c4a9354c13
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Replaced PCLinkX registers with a +2/4 adder in the execution stage.
David and I estimate this is lower hardware cost.
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2023-02-03 18:19:47 -06:00 |
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Ross Thompson
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6dcce8389a
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Change CurrPtr to Ptr in RAS.
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2023-02-03 17:40:20 -06:00 |
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Kevin Kim
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c694bde104
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Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
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2023-02-03 18:39:26 +00:00 |
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Kevin Kim
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8c9107ffa4
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arch32ba includes the 32i_m tests instead of 64
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2023-02-03 17:40:02 +00:00 |
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Kip Macsai-Goren
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1096a4e2a5
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-03 09:31:06 -08:00 |
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David Harris
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ed02d5a077
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Removed redundant line from synthesis makefile
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2023-02-03 08:36:51 -08:00 |
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David Harris
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d7ae05ae8e
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-03 08:36:11 -08:00 |
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David Harris
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398992db3b
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Updated division radix test script with paths, but script is out of date for files it manipulates
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2023-02-03 08:36:03 -08:00 |
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Kevin Kim
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c7ce9242cb
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Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
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2023-02-03 16:00:36 +00:00 |
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Kevin Kim
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ac9e672e3e
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ALU changes (ZBB)
- handles inverted operand instructions
- handles shift-and-add instructions
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2023-02-03 16:00:32 +00:00 |
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David Harris
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02bdaf858c
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Merge pull request #54 from ross144/main
Fixed issue #50, itlb and dcache flush interlock
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2023-02-03 06:30:30 -08:00 |
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Ross Thompson
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370931c1cd
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Fixed bug #49.
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
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2023-02-03 00:39:26 -06:00 |
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Ross Thompson
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a4907b5d29
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Lee Moore found another bug using imperas.
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
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2023-02-02 23:52:21 -06:00 |
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Kevin Kim
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cb6e80a62b
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Merge branch 'openhwgroup:main' into main
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2023-02-02 21:41:55 -08:00 |
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Kevin Kim
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dd4f8c0712
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Started Zbb
-Performs byte instructions (orc.b, rev8 (32/64))
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2023-02-03 05:40:38 +00:00 |
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Kevin Kim
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ea98fdd7e4
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zbs minor lint fix
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2023-02-03 05:31:50 +00:00 |
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Kevin Kim
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441282f383
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zbc initial done; passes lint.
clmul logic changes have not verified yet
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2023-02-03 04:48:23 +00:00 |
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David Harris
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a9226e6f73
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Removed lab1matrix solutions
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2023-02-02 19:40:41 -08:00 |
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Kevin Kim
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34eb33a5e7
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added bit reverse module, passes lint
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2023-02-02 23:10:57 +00:00 |
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David Harris
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aae035226f
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Merged with memories
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2023-02-02 14:50:46 -08:00 |
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David Harris
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8078cafa27
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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David Harris
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99d179dd3e
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Removed pipelined level of hierarchy
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2023-02-02 14:14:11 -08:00 |
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David Harris
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be618a0c34
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Update README.md
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2023-02-02 12:59:28 -08:00 |
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Kevin Kim
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1b6aca189d
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started zbc
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2023-02-02 20:11:11 +00:00 |
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Kevin Kim
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d498d2b2ff
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zbs passes lint
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2023-02-02 20:04:38 +00:00 |
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James E. Stine
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2a87495642
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Merge pull request #52 from stineje/main
Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
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2023-02-02 13:55:17 -06:00 |
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James Stine
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bfa69ea2b3
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Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22
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2023-02-02 13:54:25 -06:00 |
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Kevin Kim
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c1ec17a7a6
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clmul finished initial hdl; passes lint
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2023-02-02 19:49:14 +00:00 |
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David Harris
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4c50166e56
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Merge pull request #51 from stineje/main
Modify generic/mem for rv32gc ram2
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2023-02-02 11:41:32 -08:00 |
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James Stine
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b66177fd87
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Modify generic/mem for rv32gc ram2
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2023-02-02 13:28:18 -06:00 |
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Kevin Kim
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655f5bbc5e
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continued clmul unit
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2023-02-02 18:54:33 +00:00 |
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David Harris
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551594e021
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-02 10:28:40 -08:00 |
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Kevin Kim
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bdd12bfec6
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started clmul
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2023-02-02 16:40:58 +00:00 |
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David Harris
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bc0ca38b2f
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Merge pull request #48 from ross144/main
Fixed bug #47, ecall and ebreak don't commit
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2023-02-02 06:58:07 -08:00 |
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Ross Thompson
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091aadff0e
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Merge branch 'main' of github.com:ross144/cvw
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2023-02-02 08:52:48 -06:00 |
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Ross Thompson
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230888db8b
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Fixed bug #47 discovered by Lee Moore.
ECALL and EBREAK do not commit their results.
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2023-02-02 08:52:06 -06:00 |
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Ross Thompson
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d62a72a76f
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-02 08:48:19 -06:00 |
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Kip Macsai-Goren
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0a6787026b
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-01 21:31:57 -08:00 |
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Kip Macsai-Goren
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26e8b85111
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added beginning of a ZBS instruction module to the ALU. Control signals still needed
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2023-02-01 21:31:25 -08:00 |
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Ross Thompson
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a8afdf1741
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-01 19:24:10 -06:00 |
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David Harris
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93f57402df
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Removed O2 from fir Makefile to be consistent with lab.
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2023-02-01 15:43:52 -08:00 |
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David Harris
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c214a9e8fc
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Merge pull request #45 from stineje/main
Update ram2 and other memories and associated wrappers
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2023-02-01 15:06:30 -08:00 |
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James Stine
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6ce80b6b8a
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Update ram2 and other memories and associated wrappers
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2023-02-01 17:03:48 -06:00 |
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Ross Thompson
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0035579553
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Minor branch predictor bug fix.
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2023-02-01 10:59:38 -06:00 |
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Ross Thompson
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2a5b6408f2
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Removed unused signal.
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2023-02-01 10:27:58 -06:00 |
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David Harris
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129380db0b
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Fixed typo in DC setup for memories
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2023-02-01 05:49:30 -08:00 |
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David Harris
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c9b56f9acc
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Only add memory libraries when targeting 28nm
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2023-02-01 05:06:56 -08:00 |
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David Harris
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73b29e1f71
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Merge pull request #36 from davidharrishmc/dev
RV32imc configuration
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2023-02-01 04:44:36 -08:00 |
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David Harris
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0280942563
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Fixed merge conflict to get synthesis working again
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2023-02-01 04:43:57 -08:00 |
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David Harris
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838bb21077
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Merge pull request #43 from mmasserfrye/main
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
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2023-02-01 04:13:37 -08:00 |
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