Noah Boorstin
5835641c6c
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
Noah Boorstin
006f8c6c71
busybear: more small updates
...
not sure what to do about MMU yet, hopefully we'll decide at saturday's meeting
2021-02-16 20:01:00 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
Ross Thompson
78db3654c6
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
...
This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
Teo Ene
a842879741
Added scripts to report power and area on a module-by-module basis
2021-02-15 12:09:33 -06:00
David Harris
f00728448a
WALLY ALU tests
2021-02-15 10:16:31 -05:00
David Harris
f6ec4a4548
Makefrag for ALU testsgen
2021-02-15 10:12:24 -05:00
David Harris
37dba8fd26
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
Domenico Ottolia
75d9091fe8
Add privileged test cases
2021-02-14 17:01:46 -05:00
Ross Thompson
3ec1f668fc
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Teo Ene
dba5ce9c8b
Due to legacy code, make pnr would print out an internal Makefile error at the end of the run. While this error was inconsequential and did not affect anything, it still needed to be removed.
2021-02-14 13:43:30 -06:00
Ross Thompson
30df1cdd25
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
Teo Ene
72dd97d9b6
sky130 18T and 15T cell libraries removed
...
Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
Teo Ene
e878a8bed2
After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to.
2021-02-14 08:58:33 -06:00
Teo Ene
f3c902450b
After going through Lab 3 again, I've decided to make small changes to the provided floorplan so that it may serve as a slighly better example of a good floorplan.
2021-02-14 04:43:07 -06:00
Teo Ene
da6e9730a0
Cleaning up my code a little bit more
2021-02-14 02:58:25 -06:00
Teo Ene
83f7cd51e5
Final changes to the lab3 branch
...
- Removed manual register file placement script, as it has been removed from lab.
- Created pre-sets that only have to be uncommented for the changing clock target portion of lab.
- Cleaned up Makefile in case anyone looks inside of it.
2021-02-14 02:01:20 -06:00
Teo Ene
86fa5210f3
Commiting sample floorplan that I failed to commit last night
2021-02-13 12:08:03 -06:00
Teo Ene
ca7ee1d670
- Cleaned up unnecessary files
...
- Pulled updates for std cells
- Fixed typo that prevented easy switching between standard cell variants
- Fixed asynchronous reset paths from not being flagged as false
2021-02-12 21:49:42 -06:00
Shreya Sanghai
30bfd7534c
added branch tests
2021-02-12 22:40:08 -05:00
Teo Ene
9c4a117ffb
When Alex taught me how to use git, he stressed the importance of good commit messages that properly describe what changes were made
2021-02-12 16:52:23 -06:00
Teo Ene
db17d59698
Fixed rm bug for Ryan
2021-02-12 16:36:04 -06:00
Teo Ene
cc077da2bb
Removed riscv-o3 module
2021-02-12 16:08:34 -06:00
Teo Ene
f25b372c32
Quick commit for Ryan / branch / debugging.
2021-02-12 16:06:02 -06:00
Noah Boorstin
7312da1a99
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
Noah Boorstin
423d3a53e5
add reference output for some tests
2021-02-12 18:33:24 +00:00
Noah Boorstin
97302dd12f
busybear: slightly neater error handling
2021-02-12 17:21:56 +00:00
bbracker
9231646fb3
bus rw bugfix and peripherals testing
2021-02-12 00:02:45 -05:00
Noah Boorstin
5bf6add635
bump into virtual/physcial memory?
2021-02-11 23:06:12 -05:00
Noah Boorstin
4427780a41
busybear: more updates
...
now gets to instruction 839037 before failing
also updates to match new gdb output format
umm there seems to be something wrong with the SSTATUS CSR. Just leaving
it out for now, will come back and check it later
2021-02-11 22:42:58 -05:00
Noah Boorstin
86fcaab831
gdb output combine script updates
...
check that everything is actually the same instruction
update to new 4-file output
this file should be finished for now
2021-02-11 14:59:15 -05:00
Tejus Rao
5158ca4220
added test cases for ADDW, SUBW, SLLW, SRLW, SRAW
2021-02-11 13:38:38 -05:00
Teo Ene
dfb7333821
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-02-10 20:49:12 -06:00
Teo Ene
8a6de4fb86
Adding coremark testbench and do files that Elizabeth has written thus far, on this account, in order to avoid merge conflicts
2021-02-10 20:48:39 -06:00
Teodor-Dumitru Ene
86fcaf0bb1
Added hex code for the pre-compiled, provided, CoreMark binary
2021-02-10 21:22:38 -05:00
Teo Ene
7ca03b2b38
Added freshly compiled CoreMark binaries (elf) and hex code (memfile) for the following extensions:
...
- RV64I
2021-02-10 20:12:07 -06:00
ethan-falicov
9edc4b6bfe
Fixed merge conflict stuff
2021-02-10 10:03:30 -05:00
ethan-falicov
7e8a58de1a
More merge conflicts yay
2021-02-10 09:54:30 -05:00
ethan-falicov
f778f464b7
Merge conflict fixing
2021-02-10 09:45:47 -05:00
ethan-falicov
06541260e0
Adding I Type test cases from Lab 1
2021-02-10 09:39:43 -05:00
David Harris
183a2dcfb5
Debugging bus interface.
2021-02-10 01:43:54 -05:00
James E. Stine
561ffcf56d
Add ppt and mp4 of wavedrom usage
2021-02-09 13:15:29 -06:00
David Harris
2357f5513b
Debugging instruction fetch
2021-02-09 11:02:17 -05:00
David Harris
63c7c18771
Fixed lw by delaying read value by one cycle
2021-02-07 23:28:21 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
Jarred Allen
403a0d033c
Fix compile error in imperas testbench
2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg
81a1eb9a74
merge conflict?
2021-02-07 02:34:49 -05:00
Noah Boorstin
01c0f9db63
Busybear: next week of updates
...
- move parsed instructions out of git, to /courses/e190ax/busybear_boot
- parsed first 1M instructions, and now parse from split GDB runs
- now at about 230k instructions, can't progress further for now since atomic instructions
aren't implemented yet
2021-02-07 03:14:48 +00:00
Jarred Allen
48ade25577
Actually run the WALLY-LOAD tests
2021-02-06 14:56:40 -05:00
Jarred Allen
edd758453e
Add test vector set for load instructions
2021-02-06 13:05:59 -05:00
