4 Commits

Author	SHA1	Message	Date
Ross Thompson	38edbde966	Renamed RW signals through the caches, bus interfaces, and IFU/LSU. ... CPU to $ is called LSURWM or IFURWF. CPU to Bus is called BusRW $ to Bus is called CacheBusRW.	2022-09-23 11:46:53 -05:00
Ross Thompson	bcca9a62c5	Fixed up IFU ahb interface names and widths.	2022-09-19 10:54:22 -05:00
Ross Thompson	cb34b7c98f	Found the ahb burst bug. ... We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.	2022-09-17 20:30:01 -05:00
Ross Thompson	0904951a8c	Oups the ahbinterface.sv was accidentally named abhinterface.sv.	2022-09-08 13:21:37 -05:00