11 Commits

Author	SHA1	Message	Date
Ross Thompson	7592a0dacb	Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.	2021-02-26 20:12:27 -06:00
David Harris	91f6858de7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00
David Harris	a44c2abb12	Minor tweaks	2021-02-02 19:44:37 -05:00
Noah Boorstin	00d9e13d68	same thing but do that right this time	2021-02-02 21:47:15 +00:00
Noah Boorstin	56ff32f857	change undefined syntax in extend.sv ... don't need verilator execption anymore	2021-02-02 21:39:20 +00:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	4fbb5f0f1b	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	c23afbda3a	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00