Github_Repos/cvw
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105 Commits

Author SHA1 Message Date
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
5a86225e1c Fix bug in cache line 2021-03-25 12:59:30 -04:00
Jarred Allen
0776127c75 Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Jarred Allen
abf9f3b3cb Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Jarred Allen
ebd2c60b74 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00