Ross Thompson
a2de53aeeb
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
2cc4d66ded
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
4aadd87679
Moved CPUBusy out of HPTW.
2022-12-11 15:48:00 -06:00
Ross Thompson
1e2180ef98
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
ec6517fadd
Fixed a bug with the hptw configuration not correctly avoiding UPDATE_PTE state.
2022-11-14 16:02:20 -06:00
David Harris
895ee3d773
Removed comment about nonexistent possible bug
2022-11-14 09:56:33 -08:00
David Harris
cae3e00751
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-14 09:52:24 -08:00
David Harris
79d416537a
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
a27b81ef90
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
3ac6514856
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
157f816cd3
HPTW cleanup
2022-11-13 04:23:23 -08:00
Ross Thompson
c2e3bad3f5
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
64b818c49a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
9b20bf341e
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
David Harris
e57083a0ef
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
68aa1434b4
Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS.
...
Don't use this commit as the rv32i tests are not passing.
2022-10-05 14:51:02 -05:00
Ross Thompson
dd00474956
Created two new pma regions for dtim and irom.
2022-08-28 13:50:50 -05:00
Ross Thompson
e3e1f29428
Reordered the adrdecs.
2022-08-28 13:38:57 -05:00
David Harris
35d0a951d2
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
David Harris
bd6f2444cd
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
David Harris
76006825b3
Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
2022-08-26 21:18:18 -07:00
David Harris
921a49921b
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
2022-08-26 21:05:20 -07:00
David Harris
460a95f99b
Added IROM and DTIM decoding to adrdecs
2022-08-26 20:45:43 -07:00
Ross Thompson
b650d7e05a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
7080fe7788
Reversed order of supported sized in adrdecs.
2022-08-23 11:14:53 -05:00
Ross Thompson
cd0da2e3b3
Updated the names of the *WriteDataM inside the LSU to more meaningful names.
...
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
2022-08-23 10:34:39 -05:00
David Harris
7151befd04
Removed FStore2 and simplified HPTW
2022-08-22 13:29:54 -07:00
Madeleine Masser-Frye
01e6d69a67
took first match out of pmpadrdec
2022-07-06 00:02:01 +00:00
David Harris
e2e63ca9a8
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
f17501ed8c
Removing unused signals
2022-05-12 14:36:15 +00:00
David Harris
4f1b0fdc64
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
Ross Thompson
285fc6fd4d
Modified clint to support all byte write sizes.
2022-03-31 11:31:52 -05:00
Ross Thompson
fe896bff8e
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
David Harris
2ea93c4ac3
adrdecs comments
2022-02-28 20:33:41 +00:00
David Harris
2de31a15da
Modified address decoder for native access to CLINT
2022-02-28 19:13:14 +00:00
David Harris
3a43450ac9
hptw cleanup for synthesis
2022-02-28 05:54:34 +00:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
David Harris
131a1a4ded
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
