David Harris
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57e1111df3
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Gave names to for loops in generate blocks for ease of reference
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2021-07-04 18:52:16 -04:00 |
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David Harris
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79ee817d91
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Reverted MIDELEG and MEDELEG to XLEN so busybear passes
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2021-06-10 23:47:32 -04:00 |
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David Harris
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9dd3857c26
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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Ross Thompson
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9e40fb072c
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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bbracker
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da22308e60
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csri lint improvement
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2021-04-15 09:05:53 -04:00 |
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bbracker
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ccff1e6c99
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rv64 interrupt servicing
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2021-04-14 10:19:42 -04:00 |
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Ross Thompson
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1e83810450
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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bbracker
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3e656fc035
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future work comment about suspicious-looking verilog in csri.sv
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2021-03-25 00:10:44 -04:00 |
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David Harris
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92bf1674b4
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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07af481b67
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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