16 Commits

Author	SHA1	Message	Date
Katherine Parry	c3d07b2c46	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
Ross Thompson	67ff8f27f4	Can now support the following memory and bus configurations. ... 1. dtim/irom only 2. bus only 3. dtim/irom + bus 4. caches + bus	2022-03-11 15:18:56 -06:00
bbracker	202bd2f8f8	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00
Ross Thompson	0bd533473c	New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.	2022-02-17 17:19:41 -06:00
Ross Thompson	4273775a2b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 14:22:19 -06:00
David Harris	510b47523a	rv32e config update	2022-02-08 17:59:50 +00:00
Ross Thompson	853a7bba18	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-08 11:36:30 -06:00
Ross Thompson	8a2ee22395	Finished merge.	2022-02-08 11:36:24 -06:00
David Harris	64e9f4c0d3	Restored E tests to makefrag	2022-02-08 16:41:11 +00:00
David Harris	c61cd55c5c	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
David Harris	0f7b8017d1	Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit	2022-02-05 05:35:51 +00:00
David Harris	72bc64ef28	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	fb041fe06a	rv32e	2022-02-04 01:56:30 +00:00
David Harris	4ba37d5cc0	Config file & wally-riscv-arch-test cleanup	2022-02-02 16:35:52 +00:00
David Harris	748375c82f	Updated configs to fix GPIO address to match FU540	2022-01-26 18:16:34 +00:00
David Harris	b63e53bbdb	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00