87 Commits

Author	SHA1	Message	Date
David Harris	dda3b441d7	Continued busdp/ebu simplification	2022-08-25 10:20:02 -07:00
David Harris	aba914ea5e	Renamed AHB signals coming out of LSU to LSH_<AHBNAME>	2022-08-25 09:52:08 -07:00
David Harris	c789b5789c	renamed GrantData to LSUGrant	2022-08-22 13:47:19 -07:00
Ross Thompson	57fcf0ef79	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
Ross Thompson	797d9e3610	Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.	2022-08-01 21:12:25 -05:00
Ross Thompson	3612db2d70	pulled swbbytemask out of subword write.	2022-08-01 20:48:45 -05:00
David Harris	5ae88dbef0	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
David Harris	72e216d053	APB CLINT passing regression	2022-07-05 15:51:35 +00:00
David Harris	abfd935e06	removed delay in ahblite	2022-07-05 04:59:28 +00:00
slmnemo	a79737e95b	Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals	2022-06-10 20:43:56 -07:00
slmnemo	5ac17eca1d	Passed Regression: Seems to work perfectly fine	2022-06-09 18:21:13 -07:00
slmnemo	a4c7d1d936	?	2022-06-09 17:50:47 -07:00
slmnemo	c4bc608268	Changes made on 9th Jun	2022-06-09 17:33:51 -07:00
slmnemo	1605544bfc	Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.	2022-06-08 17:34:02 -07:00
slmnemo	655266a216	Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending	2022-06-08 15:59:15 -07:00
slmnemo	a64e65e54c	Fixed ifu displaying LSU bus state in wave.do	2022-06-08 15:30:32 -07:00
slmnemo	dd33f2a009	Working version: Fixed error where Word count would always increment even without AHB to bus ACK	2022-06-08 15:29:32 -07:00
slmnemo	be658d3933	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
slmnemo	1d22fc707a	Added lock signal to ensure AHB speaks with the right bus	2022-06-08 02:19:21 +00:00
slmnemo	90c5e5d319	Reworked bus to handle burst interfacing	2022-06-07 11:22:53 +00:00
slmnemo	56121b3587	Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access	2022-05-31 16:33:05 -07:00
slmnemo	2b80788235	Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode	2022-05-31 15:57:55 -07:00
slmnemo	c24f88c2e9	Redid the FSM to prepare for burst mode implementation	2022-05-31 15:57:42 -07:00
slmnemo	f426850bc7	Reverted incorrect Ack	2022-05-28 10:06:26 +00:00
slmnemo	bddc32ed21	changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word	2022-05-26 18:41:27 -07:00
slmnemo	efce3e4953	added LSUBurstDone signal to signal when a burst has finished	2022-05-26 16:29:13 -07:00
slmnemo	80965f953c	added burst size signals to the IFU, EBU, LSU, and busdp	2022-05-25 18:02:50 -07:00
slmnemo	95d64fe4ae	idk lol it says this has an unadded change	2022-05-25 17:17:49 -07:00
slmnemo	4a2538455d	added documentation for ahblite burst types to ahblite.sv	2022-05-19 18:31:46 -07:00
David Harris	f3c7025ade	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	b0263012e8	LSU cleanup	2022-01-15 00:11:30 +00:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	2df92af488	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00