16 Commits

Author	SHA1	Message	Date
Ross Thompson	4720b28272	Formatting progress.	2023-01-17 22:10:31 -06:00
Ross Thompson	d21eef40d7	Added comments to dtim and ahbcacheinterface.	2023-01-17 21:56:55 -06:00
David Harris	17fd2d2a3b	ebu cleanup	2023-01-14 19:19:34 -08:00
David Harris	b4dd7b21e6	generic cleanup	2023-01-14 19:02:38 -08:00
David Harris	7d93659f6b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	5fbba604f1	Remove unused CACHE_ENABLED parameter	2023-01-07 09:57:24 -08:00
Ross Thompson	6d573b32d2	Changed CPUBusy to Stall in ebu modules.	2022-12-11 15:51:35 -06:00
Ross Thompson	54544ae251	Moved all remaining bus logic from the LSU into ahbcacheinterface.	2022-11-11 14:30:32 -06:00
Ross Thompson	8658a25218	Renamed Word to Beat for ahbcacheinterface.	2022-11-09 17:52:50 -06:00
Ross Thompson	be8e0eee1b	Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). ... FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS. FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to not stall W if we get a trap.	2022-11-07 15:50:55 -06:00
Ross Thompson	65c2fe294a	Merged cacheable with seluncachedadr.	2022-10-17 13:29:21 -05:00
Ross Thompson	38edbde966	Renamed RW signals through the caches, bus interfaces, and IFU/LSU. ... CPU to $ is called LSURWM or IFURWF. CPU to Bus is called BusRW $ to Bus is called CacheBusRW.	2022-09-23 11:46:53 -05:00
Ross Thompson	12d1ef2144	More renaming.	2022-08-31 14:49:08 -05:00
Ross Thompson	c03b202ab0	Moved files. ... Encapsulated ahbinterface.	2022-08-31 14:45:01 -05:00