Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
6,609 Commits 5 Branches 2 Tags 53 MiB
44c72c20e2
Commit Graph

173 Commits

Author SHA1 Message Date
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Ross Thompson
d79c084a70 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
7ac5239d6a Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
19b7819d53 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
7fb58f5cac more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
8caa4dfcfb Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
005307fc16 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
5d0e86f650 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
ed7d785175 Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
5b0467b287 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
7d53af9206 Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
269d7b2430 More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
40f7031fe7 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
261b34af5d The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
Ross Thompson
d9f7daf5e0 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
80a6170fe1 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
bbe3f1caf0 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00
Ross Thompson
9a1042b0b1 This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
Ross Thompson
74ccabdf69 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
f4883e31df
Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
Ross Thompson
822e60bd3d Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
David Harris
436ba397ce Support all testfloat tests with parameterized design 2023-05-31 06:30:21 -07:00
Ross Thompson
0f8049a04f Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
Ross Thompson
903f2f9063 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
6509463f3d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
c5aeb08e5c Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
485508274e
Merge pull request #297 from davidharrishmc/dev 
Verilator testbench changes
 2023-05-22 13:29:54 -04:00
David Harris
533ddf5eb3 Removed force from branch predictor initialization 2023-05-22 09:57:41 -07:00
David Harris
f257259045 Initial testbench cleanup for Verilator 2023-05-22 09:51:46 -07:00
Ross Thompson
1dc7fb567b Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
David Harris
d086dbffb4 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
e34b25511a Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
35a59a1193 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
799c25cc60 Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Kevin Wan
3569998cb9 fixed tests.vh test lines 2023-04-28 07:47:59 -07:00
Kevin Wan
c0cbd0fd2a added tests for pmppriority module 2023-04-27 16:12:43 -07:00
Noah Limpert
26cb639f89 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Noah Limpert
cf150a2ea9 Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
73cca666bf Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
68295bd750
Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
59d153ace0
Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
a13feb5d0b
Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
Alec Vercruysse
3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
2a4bc01944 Update tests.vh 2023-04-18 23:15:47 -07:00
Kevin Wan
20a0803f46 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Kevin Thomas
385564fe4c Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00