Kevin Kim
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b81a5e4452
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added BRegWriteE signal
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2023-03-02 12:15:22 -08:00 |
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Kevin Kim
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5e10720bed
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rename shifternew to shifter
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2023-03-02 11:45:32 -08:00 |
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Kevin Kim
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cf324510f3
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zbc input select mux optimize
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2023-03-02 11:43:05 -08:00 |
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Kevin Kim
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657719220a
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zbc select mux optimization
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2023-03-02 11:40:29 -08:00 |
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Kevin Kim
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e62a752522
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fixed controller lint, changed byte unit mux select name and input width
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2023-03-02 11:36:12 -08:00 |
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Kevin Kim
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a5e2e24320
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removed redundant zbs
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2023-03-02 11:22:09 -08:00 |
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Ross Thompson
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9bd6851ed5
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Merge pull request #123 from eroom1966/main
fix the memory map privileges in the REF model view
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2023-03-02 09:27:35 -06:00 |
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eroom1966
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fe4d9d3e37
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fix the memory map privileges in the REF model view
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2023-03-02 15:25:27 +00:00 |
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Ross Thompson
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b98e007a53
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Cleaned up branch predictor performance counters.
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2023-03-01 17:05:42 -06:00 |
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David Harris
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5c8c50adba
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-03-01 11:18:05 -08:00 |
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David Harris
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23775c6d67
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Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA
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2023-03-01 11:18:00 -08:00 |
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David Harris
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a7b15c4503
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Merge pull request #121 from ross144/main
Branch predictor cleanup. Chapter 10 now matches the hardware
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2023-03-01 09:57:59 -08:00 |
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Ross Thompson
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90b2f0a652
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Set bp to use instruction class prediction by default.
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2023-03-01 11:52:42 -06:00 |
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Ross Thompson
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dea6b643a6
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Branch predictor cleanup.
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
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2023-03-01 11:24:24 -06:00 |
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Ross Thompson
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03a6679ba0
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More btb cleanup.
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2023-03-01 10:47:00 -06:00 |
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Ross Thompson
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554e7d0973
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Minor fix to btb.
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2023-03-01 10:45:40 -06:00 |
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Ross Thompson
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093d190c9a
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-03-01 10:04:13 -06:00 |
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Ross Thompson
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6880a052e0
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Merge pull request #119 from eroom1966/main
update ImperasDV testbench for memory privileges
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2023-03-01 09:50:00 -06:00 |
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Ross Thompson
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f141ec2777
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Merge pull request #118 from davidharrishmc/dev
Pulled to latest commit of riscv-arch-test
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2023-03-01 09:49:19 -06:00 |
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eroom1966
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f86a12f282
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update testbench for memory privileges
also update configuration to define value of mimpid
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2023-03-01 15:37:11 +00:00 |
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Ross Thompson
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a6917d07f3
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Name cleanup.
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2023-02-28 17:48:58 -06:00 |
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David Harris
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906e74dac2
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Pulled to latest commit of riscv-arch-test
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2023-02-28 15:03:59 -08:00 |
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Kip Macsai-Goren
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58ab6ec805
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Merge remote-tracking branch 'upstream/main' into bit-manip
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2023-02-28 14:41:51 -08:00 |
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Kip Macsai-Goren
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f63748f097
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Merge remote-tracking branch 'origin' into bit-manip
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2023-02-28 14:39:57 -08:00 |
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Ross Thompson
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4c0e7f297a
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Found the performance bug with the branch predictor btb power saving update.
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2023-02-28 15:57:34 -06:00 |
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Ross Thompson
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2ebe600f54
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Name changes to reflect diagrams.
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2023-02-28 15:37:25 -06:00 |
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Ross Thompson
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be4823f7dd
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Undid the btb update as it reduces performance.
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2023-02-28 15:21:56 -06:00 |
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Kevin Kim
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df0d75034b
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bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG]
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2023-02-28 12:09:35 -08:00 |
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Kevin Kim
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b61d881c1b
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added BRegWrite, BW64, BALUOp signals to bctrl and controller
-TODO: Main decode in bmuctrl must assert these 3 signals
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2023-02-28 11:54:10 -08:00 |
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Kevin Kim
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692e406976
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changed shifter source select signal name
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2023-02-28 11:41:40 -08:00 |
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Kevin Kim
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1506d50c63
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rename result back to ALUResult in ALU
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2023-02-28 07:27:34 -08:00 |
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Ross Thompson
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9dd3379744
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This icpred and btb changes are causing a performance issue.
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2023-02-27 20:00:50 -06:00 |
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Ross Thompson
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544abe2819
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Modified the BTB to save power by not updating when the prediction is unchanged.
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2023-02-27 17:37:29 -06:00 |
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Ross Thompson
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bc5aecf948
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-27 09:48:03 -06:00 |
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Ross Thompson
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c5d98d5465
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Merge pull request #117 from davidharrishmc/dev
ZMMUL support and MMU cleanup
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2023-02-27 09:46:40 -06:00 |
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David Harris
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cf8b5f0783
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Added support for ZMMUL
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2023-02-27 07:29:53 -08:00 |
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Ross Thompson
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318189e5e6
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Signal name changes.
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2023-02-27 00:39:19 -06:00 |
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David Harris
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f40352e82b
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hptw typo fix
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2023-02-26 19:38:34 -08:00 |
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Ross Thompson
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c89812b2d4
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Branch predictor cleanup.
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2023-02-26 21:28:36 -06:00 |
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David Harris
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e9ad6ae057
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Simplified Access fault logic in HPTW
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2023-02-26 18:50:37 -08:00 |
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David Harris
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5ae3dd77f9
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-26 18:35:14 -08:00 |
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David Harris
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2d7145901b
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StoreAmo faults are generated instead of load faults on AMO operations
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2023-02-26 18:35:10 -08:00 |
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Ross Thompson
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e8c5e5b5ff
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Create module for instruction class prediction and decoding.
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2023-02-26 20:20:30 -06:00 |
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Ross Thompson
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3964ce3309
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-26 19:58:24 -06:00 |
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David Harris
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21b28fd1bb
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Renamed DAPageFault to UpdateDA
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2023-02-26 17:51:45 -08:00 |
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David Harris
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4274071333
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renamed UpperBitsUnequalPageFault to UpperBitsUnequal
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2023-02-26 17:32:34 -08:00 |
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David Harris
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06bd4783af
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moved tlb to subdirectory
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2023-02-26 17:31:03 -08:00 |
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David Harris
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c774b44116
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Moved TLB into subdirectory of MMU
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2023-02-26 17:28:05 -08:00 |
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Ross Thompson
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ad462388cb
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Merge pull request #116 from davidharrishmc/dev
Removed unneeded TLBFlush from TLBMiss logic
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2023-02-26 12:07:41 -06:00 |
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Ross Thompson
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72be4318b8
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-02-26 12:06:06 -06:00 |
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