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3,265 Commits 5 Branches 2 Tags 53 MiB
3f2ec0499f
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6 Commits

Author SHA1 Message Date
David Harris
3f2ec0499f Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
Ross Thompson
b2a77da96b Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
Ross Thompson
bdfca503fa Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
d5f524a15e Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
Ross Thompson
e00d404154 More cache cleanup. 2022-02-10 10:43:37 -06:00