Commit Graph

104 Commits

Author SHA1 Message Date
Alec Vercruysse
de93bd6937 D$ scope-specific coverage exclusions (I$ logic that never fires)
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Alec Vercruysse
9ef85c547b fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
David Harris
64fe318cb0 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Ross Thompson
30e3d2cdce Merge pull request #233 from AlecVercruysse/coverage3
Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
David Harris
48de682ea8 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
21db7a0d68 fdivsqrtfsm coverage attempt to waive a state 2023-04-13 17:40:14 -07:00
David Harris
5066cd99ab Merge pull request #237 from SydRiley/main
fctrl coverage at 100% after removing redundancies from conditionals
2023-04-13 17:10:46 -07:00
Limnanthes Serafini
1d72e56fec Merge branch 'openhwgroup:main' into cachesim 2023-04-13 16:54:35 -07:00
Limnanthes Serafini
95586abe09 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
034c289a36 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Sydeny
2b8891cefd Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Alec Vercruysse
680aee7e07 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
ad0e366766 track GetLinenum.do (tcl procedure to find line numbers to exclude) 2023-04-12 15:58:38 -07:00
Alec Vercruysse
01f2417524 cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
James E. Stine
001a364d6c Modification to testfloat.do to accept argument for nowave or by default none 2023-04-12 14:49:40 -05:00
Ross Thompson
10be07857c Merge pull request #229 from davidharrishmc/dev
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
2023-04-12 12:21:03 -05:00
Alec Vercruysse
1cb6e1751b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
Limnanthes Serafini
3f9a22e8d4 Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
e6cb928ab2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
095f3d5542 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
4cbb9bcec6 refactor cachefsm to get full coverage
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
2023-04-12 01:15:35 -07:00
James Stine
744e170be3 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
Limnanthes Serafini
e6a9d236b5 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
David Harris
a34867d14e Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic. ImperasDV is happy with these privileged tests now 2023-04-10 07:05:06 -07:00
eroom1966
dc79710724 add support into configuration for Zb(a,b,c,s) 2023-04-06 16:30:14 +01:00
eroom1966
adafc8037d add support for Sstc 2023-04-04 17:20:00 +01:00
David Harris
a6117e9bef Updated imperas.ic to enable B extension 2023-04-03 17:55:30 -07:00
David Harris
c1ec1cb09c Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests 2023-03-31 10:54:03 -07:00
David Harris
60a8a26f2e regression cleanup; unable to run buildroot coverage because of different config file 2023-03-31 09:59:38 -07:00
David Harris
69805b4a60 Regression update 2023-03-31 09:15:15 -07:00
David Harris
fd0c9e973d Coverage improvements in ieu, hazard units 2023-03-31 08:33:46 -07:00
Alec Vercruysse
a7066a20f1 add tests/coverage/ tests as a target to sim/Makefile 2023-03-27 14:02:30 -07:00
David Harris
a0504fd70c Commented out setting RISCV in run-imperas-linux.sh 2023-03-27 06:34:45 -07:00
eroom1966
1a10e48ecf update to allow running of ImperasDV with linux boot
optimize performance of the tracer
2023-03-27 09:46:16 +01:00
Lee Moore
4bb7dadc00 Merge branch 'openhwgroup:main' into add-linux 2023-03-27 09:44:13 +01:00
David Harris
2dda311df8 Avoid printing junk when running regression 2023-03-24 08:11:15 -07:00
David Harris
b674ebf7f4 100% IEU coverage 2023-03-23 17:25:27 -07:00
David Harris
121d1cea62 Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
David Harris
f4b252522e Coverage improvements 2023-03-23 09:06:05 -07:00
David Harris
ba4e0d2721 Merged bit manip 2023-03-23 06:55:29 -07:00
Kevin Kim
16a7236ac8 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 15:38:11 -07:00
James Stine
a4e5abad22 Change order of coverage and all in sim directory - order causing issue with compilation process of regression tests 2023-03-22 16:23:27 -05:00
Kip Macsai-Goren
8ef5422f67 fixed sim-wally-batch 2023-03-22 14:16:07 -07:00
Kip Macsai-Goren
03472ec7bb restored sim-wally-batch to existing tests 2023-03-22 13:32:24 -07:00
David Harris
3b3aa942c7 Added coverage tests to regression coverage 2023-03-22 13:00:10 -07:00
Kevin Kim
1eb96e2221 Merge branch 'openhwgroup:main' into bit-manip 2023-03-22 10:33:15 -07:00
eroom1966
259fbc8d77 support linux 2023-03-22 17:10:32 +00:00
David Harris
f6bc499f34 Testbench improvements for coverage reporting and running Imperas suite to raise test coverage 2023-03-22 04:34:49 -07:00