Ross Thompson
693f32973f
Minor optimizations.
2022-12-23 20:11:36 -06:00
Ross Thompson
f4f68cdd19
Improved comment.
2022-12-23 15:13:15 -06:00
Ross Thompson
b5a85b55f1
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
5a9e94048a
The LSU is properly using FlushW rather than TrapM.
2022-12-22 21:47:34 -06:00
Ross Thompson
ce7e1073fa
Success we've replaced TrapM with FlushD in the IFU.
2022-12-22 21:36:49 -06:00
David Harris
aac4b55b59
Explained hazard causes
2022-12-19 09:41:41 -08:00
Ross Thompson
ddde82f928
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
David Harris
a8126458f6
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
Ross Thompson
8cd6a74c8f
Hazard cleanup.
2022-12-15 10:05:17 -06:00
Ross Thompson
c253b882be
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
Ross Thompson
0f0fed2496
Broken dont' use.
2022-12-11 23:24:01 -06:00
Ross Thompson
dbc3dac03d
Removed unused flushf.
2022-12-11 16:28:11 -06:00
David Harris
3a07d56d33
Renamed FPUStallD to FCvtIntStallD
2022-12-02 11:55:23 -08:00
David Harris
db5f3c15a4
FPU divider working with execute stage stall
2022-12-02 11:11:53 -08:00
David Harris
1bd639be6d
code cleanup
2022-12-01 08:15:48 -08:00
Ross Thompson
421c6f9c48
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
2ebdfa3f68
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
Ross Thompson
4db912678d
Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.
2022-10-22 16:27:20 -05:00
Ross Thompson
47608df73e
Possible fix for interrupt during a floating point divide.
2022-10-18 15:04:21 -05:00
Ross Thompson
e7de0e033e
Added comments about planned changes.
2022-08-29 09:48:00 -05:00
David Harris
d556adde16
Simplified FPU-LSU interface to skip IEU
2022-08-22 13:28:51 -07:00
Katherine Parry
75a8cea4e4
srt divider merged into fpu
2022-07-07 16:01:33 -07:00
DTowersM
38382e3a11
added #1 delays to Stalls and Flushes in hazard unit
2022-06-08 16:28:09 +00:00
David Harris
9065b684f8
Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
2022-06-02 09:37:59 -07:00
David Harris
7cf5d481c0
Cleaned up comments in controller
2022-06-02 15:48:33 +00:00
David Harris
129fab3794
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
David Harris
4335895b21
Added comments to some files, added a+b = 0 detector to comparator.sv
2022-05-28 09:41:48 +00:00
David Harris
9f8dca5190
Moved TLB Flush logic into privdec
2022-05-12 16:41:52 +00:00
David Harris
2cdd49c7d2
WFI terminates when an interrupt is pending even if interrupts are globally disabled
2022-05-08 04:30:46 +00:00
David Harris
c100c9893b
wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
2022-05-05 14:37:21 +00:00
David Harris
94459ade3d
Changed WFI to stall pipeline in memory stage
2022-05-05 02:03:44 +00:00
David Harris
03f84bf11c
Extended sim time to fully boot Linux. Added comments to hazard unit
2022-04-24 13:51:00 +00:00
David Harris
d9e8d16bbe
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
93cb24476f
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
David Harris
3d2671a8b0
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
2df92af488
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
115287adc8
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
