bbracker
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cc91c774a6
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Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
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2021-06-08 12:41:25 -04:00 |
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bbracker
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e7e4105931
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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Kip Macsai-Goren
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c96695b1b6
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implemented simpler page mixers, cleaned up a bit
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2021-06-07 18:32:34 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Katherine Parry
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75a6097467
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fixed lint warnings for fpu and lzd
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2021-06-05 12:06:33 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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Katherine Parry
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fc65aedbd6
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Double-precision FMA instructions
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2021-06-04 14:00:11 -04:00 |
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Kip Macsai-Goren
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1ea9b94cf1
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added tests for SV48 and translation off with vmem
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2021-06-03 14:28:52 -04:00 |
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James E. Stine
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2eeb12c674
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Updates to muldiv.sv for 32-bit div/rem
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2021-06-01 15:31:07 -04:00 |
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Ross Thompson
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89ad4477e4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-01 11:33:12 -05:00 |
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Ross Thompson
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857f59ab5c
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Now have global history working correctly.
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2021-06-01 10:57:43 -05:00 |
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James E. Stine
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ddbdd0d5a2
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Modify muldiv.sv to handle W instructions for 64-bits
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2021-05-31 23:27:42 -04:00 |
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bbracker
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39ae743543
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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Katherine Parry
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778ba6bbf5
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classify unit created and passes imperas tests
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2021-05-27 18:53:55 -04:00 |
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Katherine Parry
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1459d840ed
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All compare instructions pass imperas tests
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2021-05-27 15:23:28 -04:00 |
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Katherine Parry
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309e6c3dc1
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FADD and FSUB imperas tests pass
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2021-05-26 12:33:33 -04:00 |
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Kip Macsai-Goren
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8ae43a15d4
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partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
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2021-05-24 20:59:26 -04:00 |
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James E. Stine
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295263e122
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Mod for DIV/REM instruction and update to div.sv unit
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2021-05-24 19:29:13 -05:00 |
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Ross Thompson
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c5310e85c1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-05-24 14:28:41 -05:00 |
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Katherine Parry
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90d5fdba04
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FMV.X.D imperas test passes
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2021-05-24 14:44:30 -04:00 |
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Ross Thompson
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8bf411c640
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Updated branch predictor tests/benchmarks.
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2021-05-24 11:13:33 -05:00 |
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Katherine Parry
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70968a4ec3
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FSD and FLD imperas tests pass
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2021-05-23 18:33:14 -04:00 |
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bbracker
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846553ac7d
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improved PLIC test organization
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2021-05-21 15:13:02 -04:00 |
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James E. Stine
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e70136ec78
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Minor testbench updates to rv64icfd
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2021-05-21 09:41:21 -05:00 |
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James E. Stine
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23769e36a5
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Update to testbench-imperase for rv64icfd
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2021-05-21 09:28:44 -05:00 |
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James E. Stine
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fed3b30557
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Update to FLD/FSD testbench
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2021-05-21 09:26:55 -05:00 |
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James E. Stine
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c89d3e01bb
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Update to rv64icfd wally-config to run through FP tests
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2021-05-21 09:22:17 -05:00 |
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Katherine Parry
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4db7f3065c
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FMV.D.X imperas test passes
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2021-05-20 22:18:33 -04:00 |
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Katherine Parry
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06af239e6c
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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bbracker
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1d3db5ead5
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small bit of busybear debug progress
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2021-05-19 20:18:00 -04:00 |
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bbracker
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979a9bf037
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commented out MSTATUS test
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2021-05-19 12:38:01 -04:00 |
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James E. Stine
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44dc665fc5
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Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
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2021-05-18 13:48:44 -05:00 |
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David Harris
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26531f2634
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fixed rv64mmu makefile
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2021-05-18 14:25:55 -04:00 |
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Katherine Parry
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9464c9022d
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floating point infinite loop removed from imperas tests
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2021-05-18 10:42:51 -04:00 |
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bbracker
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f00eb22700
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fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
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2021-05-17 19:25:54 -04:00 |
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bbracker
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e4c90f503a
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regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
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2021-05-17 18:44:47 -04:00 |
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James E. Stine
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daf780b9c2
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Mod Imperas Testbench for updated Div/Rem
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2021-05-17 16:56:30 -05:00 |
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Domenico Ottolia
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88ab07d456
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Forgot to add csr permission tests to testbench
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2021-05-04 20:20:22 -04:00 |
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ushakya22
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682bc7b58e
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Added mip tests to testbench
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2021-05-04 15:36:06 -04:00 |
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Domenico Ottolia
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8398e653dd
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Re-add medeleg tests to testbench
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2021-05-04 14:42:20 -04:00 |
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ushakya22
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46f20745d7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-04 02:22:17 -04:00 |
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ushakya22
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b805b98a8c
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Added MIE tests to testbench
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2021-05-04 02:22:01 -04:00 |
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Domenico Ottolia
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1673ad6e27
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Minor tweaks to mcause & scause tests
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2021-05-04 01:33:49 -04:00 |
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David Harris
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45b0af497c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-04 01:19:57 -04:00 |
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David Harris
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d68fe44446
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Fixed testbench to produce error when signature.output doesn't exist
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2021-05-04 01:19:44 -04:00 |
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Thomas Fleming
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41a19153cc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-05-04 01:14:13 -04:00 |
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Domenico Ottolia
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67c7bfe34d
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Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE
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2021-05-04 01:04:12 -04:00 |
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