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6 Commits

Author SHA1 Message Date
Ross Thompson
27e32980ad cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
3dbf6790e1 Towards allowing dtim + bus. 2022-03-11 14:58:21 -06:00
Ross Thompson
11e5aad38a Moved subcachelineread inside the cache. There is some ugliness to still resolve. 2022-03-11 12:44:04 -06:00
David Harris
48705457d5 LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
Ross Thompson
308cc34d6f Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
Ross Thompson
f6f0539e10 Got separate module for the sub cache line read. 2022-02-04 20:23:09 -06:00