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259 Commits

Author SHA1 Message Date
Ross Thompson
74834bde2c Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
0394f3232f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
34ce25ca81 Commented SVADU requirements for wally32priv mmu tests 2023-07-04 11:34:07 -07:00
David Harris
4c921fc797 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
James E. Stine
407bf44548 Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion. 2023-06-29 08:46:11 -05:00
James E. Stine
012316aa94 Minor tweak to fix vectors not working for fadd. 2023-06-26 14:25:44 -05:00
James E. Stine
83a79b3a40 Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly 2023-06-26 10:14:49 -05:00
James E. Stine
e913c1ea46 Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works 2023-06-22 15:27:17 -05:00
James E. Stine
394c7ac9af Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
1d2eb60ffb Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
60931e7d5c Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
David Harris
e2f927b4e6 Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
Ross Thompson
4bee446cad Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
David Harris
dfedc13cfc erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00
David Harris
281c036e70
Merge pull request #342 from ross144/main 
Testbench generates embench output files
 2023-06-16 10:32:18 -07:00
Ross Thompson
509aee36ef Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
David Harris
2d94800ad7 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:03:48 -07:00
David Harris
1cb0cf38b4
Merge pull request #341 from ross144/main 
Fix embench so it does not crash
 2023-06-16 10:03:41 -07:00
Ross Thompson
3f628d6bf2 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
David Harris
3c98ed9e29 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
eroom1966
9125f25880 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Ross Thompson
605ddf7990 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
Ross Thompson
110a41c046 Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
34d1d50b87 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
a55bcad5c1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
3c4677ef63 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
44c72c20e2 Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
David Harris
bcb9c242d4 Added BMU instructions to instruction name decoder 2023-06-15 09:26:09 -07:00
Ross Thompson
d79c084a70 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
7ac5239d6a Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
19b7819d53 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
7fb58f5cac more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
8caa4dfcfb Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
005307fc16 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
5d0e86f650 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
ed7d785175 Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
5b0467b287 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
7d53af9206 Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
269d7b2430 More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
40f7031fe7 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
261b34af5d The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
David Harris
b83d483c9d
Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
Ross Thompson
d9f7daf5e0 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
80a6170fe1 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
bbe3f1caf0 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00
Ross Thompson
9a1042b0b1 This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
eroom1966
b0f9c77156 Update for new layout of ImperasDV files 2023-06-12 09:29:07 +01:00
Ross Thompson
987e5a5bf0 Removed comments around commented code for verilator. 2023-06-11 15:30:51 -05:00
Ross Thompson
1bf57e3dd1 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
James E. Stine
eded0c6fbe Update testbench-fp thanks to Kevin's help - also fixed add which was broken due to config 2023-06-11 15:15:47 -05:00
David Harris
9373ad3811 Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
Ross Thompson
74ccabdf69 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
f4883e31df
Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
Ross Thompson
822e60bd3d Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
80cdb02d43 Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
David Harris
436ba397ce Support all testfloat tests with parameterized design 2023-05-31 06:30:21 -07:00
Ross Thompson
0f8049a04f Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
Ross Thompson
903f2f9063 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
6509463f3d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
c5aeb08e5c Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
485508274e
Merge pull request #297 from davidharrishmc/dev 
Verilator testbench changes
 2023-05-22 13:29:54 -04:00
David Harris
533ddf5eb3 Removed force from branch predictor initialization 2023-05-22 09:57:41 -07:00
David Harris
f257259045 Initial testbench cleanup for Verilator 2023-05-22 09:51:46 -07:00
Ross Thompson
1dc7fb567b Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
David Harris
d086dbffb4 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
e34b25511a Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
35a59a1193 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
799c25cc60 Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Kevin Wan
3569998cb9 fixed tests.vh test lines 2023-04-28 07:47:59 -07:00
Kevin Wan
c0cbd0fd2a added tests for pmppriority module 2023-04-27 16:12:43 -07:00
Noah Limpert
26cb639f89 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Noah Limpert
cf150a2ea9 Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
73cca666bf Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
68295bd750
Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
59d153ace0
Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
a13feb5d0b
Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
Alec Vercruysse
3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
2a4bc01944 Update tests.vh 2023-04-18 23:15:47 -07:00
Kevin Wan
20a0803f46 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Kevin Thomas
385564fe4c Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Limnanthes Serafini
4ec28ef32d
Merge branch 'openhwgroup:main' into code_quality 2023-04-13 19:59:58 -07:00
Limnanthes Serafini
6fddc591b5 Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
Limnanthes Serafini
99cd913d75 Further indents 2023-04-13 19:07:43 -07:00
Limnanthes Serafini
0862688168 testbench code visual improvements 2023-04-13 19:06:09 -07:00
David Harris
fe083e1edc
Merge pull request #243 from Noah-G-L/main 
Pull Request to add tlbKP.S - Fill in cache lines
 2023-04-13 18:13:04 -07:00
Limnanthes Serafini
51f6561476 A couple indents->spaces 2023-04-13 17:00:41 -07:00
Noah Limpert
419377a8f8 git did not seem to add tests.vh, trying again 2023-04-13 16:59:10 -07:00
Limnanthes Serafini
e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
ecce9b0ce1 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
David Harris
3b6e397172 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
David Harris
c5e3b5c68d Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
James Stine
f5201da676 Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00