17 Commits

Author	SHA1	Message	Date
eroom1966	5f358d1af7	add changes for latest IDV file layout	2023-06-16 16:43:53 +01:00
Ross Thompson	d46500bfe0	Fixed the imperas testbench to work with parameters.	2023-06-16 08:59:52 -05:00
eroom1966	47999784d6	fix break to simulation testbench	2023-04-06 14:45:41 +01:00
eroom1966	adafc8037d	add support for Sstc	2023-04-04 17:20:00 +01:00
Ross Thompson	0afba56927	Updated GPIO signal names to reflect book.	2023-03-24 18:55:43 -05:00
eroom1966	9ddfe52c9f	Fix MISA RO and UART addresses ... It appears on inspection that the MISA register is read only in Wally In which case this has now also been set in the ImperasDV representation Also the Addresss for the UART R/W privileges are corrected	2023-03-13 11:07:19 +00:00
eroom1966	0233130d9c	Enhancements to support the PMA ranges	2023-03-10 14:09:22 +00:00
eroom1966	39ac3cd18f	Add support for setting PMP registers ... Add support for async DV	2023-03-08 12:44:53 +00:00
eroom1966	fe4d9d3e37	fix the memory map privileges in the REF model view	2023-03-02 15:25:27 +00:00
eroom1966	f86a12f282	update testbench for memory privileges ... also update configuration to define value of mimpid	2023-03-01 15:37:11 +00:00
eroom1966	dcfa153100	add support for idv package	2023-02-22 13:27:01 +00:00
David Harris	9d83749ca6	moved riscvassertons to its own file, added proper license headers to testbench support files	2023-02-16 19:40:27 -08:00
eroom1966	237a115377	add files to support coverage	2023-02-15 11:13:50 +00:00
eroom1966	ae3ac02556	remove dead code for ignoring fflags/fcsr	2023-02-06 15:53:29 +00:00
eroom1966	232bfbcfd0	remerge changes	2023-02-06 13:43:12 +00:00
David Harris	b09002c71d	Fixed license on testbench files	2023-02-04 08:19:20 -08:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00