Github_Repos/cvw
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3 Commits

Author SHA1 Message Date
Rose Thompson
8ca565ed53 Updated for a better ILA rvvi debugger. 2024-07-22 17:44:04 -05:00
Rose Thompson
121342f4cc Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Rose Thompson
24609f0b7f Now have configurations to switch between supporting RVVI over ethernet. 2024-07-22 10:51:13 -05:00