5 Commits

Author	SHA1	Message	Date
Rose Thompson	6a4c8667df	Added new signals to ILA to debug the RVVI tracer. ... The tracer appears to be stuck and the CPU is never getting out of (into reset).	2024-05-30 16:43:25 -05:00
Rose Thompson	9703055758	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
Rose Thompson	7693c5d4e2	Updates to fpga top level.	2023-12-15 15:32:05 -06:00
Rose Thompson	26cd22c388	Replaced fpga's verilog top with system verilog.	2023-12-15 13:42:52 -06:00
Rose Thompson	dab9d7ab3c	Replaced fpga top level verilog with system verilog.	2023-12-15 13:07:08 -06:00