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186 Commits 5 Branches 2 Tags 53 MiB
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10 Commits

Author SHA1 Message Date
David Harris
d00d42cf9a Merged bus into main 2021-02-25 00:28:41 -05:00
David Harris
c52a99ce2d Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
8dec69c2ce Added MUL 2021-02-15 22:27:35 -05:00
David Harris
37dba8fd26 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
David Harris
183a2dcfb5 Debugging bus interface. 2021-02-10 01:43:54 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
David Harris
4fbb5f0f1b Cleaned up hazard interface 2021-02-02 13:53:13 -05:00
David Harris
c23afbda3a Moved LoadStall generation to IEU 2021-02-02 13:42:23 -05:00
David Harris
9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00