Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
6,608 Commits 5 Branches 2 Tags 53 MiB
2fc8080102
Commit Graph

611 Commits

Author SHA1 Message Date
Ross Thompson
6e6185743a Merge branch 'main' into localhistory 2023-05-01 10:35:50 -05:00
David Harris
c1786bfec8 IMMU exclude non word-sized accesses 2023-05-01 08:14:19 -07:00
Ross Thompson
f1038f1eec Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-30 23:30:13 -05:00
David Harris
bfa35d727b Fixed redundant check of SupportedFmt on fmv that caused coverage problem on fctrl 2023-04-29 05:58:40 -07:00
David Harris
d5c350c597 Merged coverage exclusions for PMP 2023-04-28 08:04:25 -07:00
David Harris
ca5a71bbe5 PMA Checker coverage 2023-04-28 07:53:59 -07:00
David Harris
22e4f82a99 Commenting 2023-04-28 07:52:08 -07:00
David Harris
f6f43e826a Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues 2023-04-28 07:03:46 -07:00
Ross Thompson
253344f491 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-27 16:38:36 -05:00
David Harris
e962e95e53 CSR code cleanup 2023-04-27 14:12:57 -07:00
David Harris
e519eaa33f Renamed byteUnit to byteop 2023-04-27 14:10:46 -07:00
Ross Thompson
8eaa4bf075 Fixed bug in cacheLRU when NUMWAYS = 2. 2023-04-27 14:30:01 -05:00
Liam
6803347a49 Pmpadrdecs test cases changing AdrMode to 2 or 3 
Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
 2023-04-27 12:23:35 -07:00
David Harris
e69ebc45c0 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-27 07:30:07 -07:00
Alexa Wright
667c54c129
Merge branch 'openhwgroup:main' into main 2023-04-26 16:26:30 -07:00
Alexa Wright
79031e3de0 Added better comment for the exclusion in privdec.sv 2023-04-26 16:25:55 -07:00
David Harris
7c1a4e5e32 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-26 15:40:11 -07:00
David Harris
0ad5165795
Merge pull request #283 from SydRiley/main 
Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
 2023-04-26 15:40:01 -07:00
Sydeny
4595c22fe1 Addressing Redundant logic around BadNanBox, fpu coverage from 96.61% to 96.77% 2023-04-26 14:35:43 -07:00
David Harris
d71d84b386 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-26 05:53:42 -07:00
Alec Vercruysse
6299c0ef0b Cacheway Exclude FlushStage=1 when SetValidWay=1 
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).

My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
 2023-04-25 20:30:46 -07:00
Alexa Wright
55a74fd315 Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00
Alec Vercruysse
2f49ee18fe Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign 
FlushWay is always 1 for one way, but by default it is only 1 for
way 0.

The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
 2023-04-25 17:02:53 -07:00
David Harris
03448aa691 Commented about Sstvecd trap vector alignment 2023-04-24 12:20:33 -07:00
David Harris
8bf9329815 Added M suffix in atomic 2023-04-24 12:19:56 -07:00
Ross Thompson
89a242d143 Might actually have a correct implementation of local history branch prediction. 2023-04-24 13:05:28 -05:00
Ross Thompson
7588de5a36 Fixed the local branch predictor so that it at least compiles. 2023-04-24 11:06:53 -05:00
Diego Herrera Vicioso
c681789296 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
David Harris
1d532dfcfc Fault on writes to odd-numbered PMPCFG in RV64 2023-04-22 15:32:39 -07:00
David Harris
a5b80bc440 Removed unproven fdivsqrt exclusion 2023-04-22 15:27:05 -07:00
David Harris
8be5ed9b67 Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
David Harris
0871bbe8f2 Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right 2023-04-22 10:07:48 -07:00
David Harris
e11212598f fdivsqrt cleanup 2023-04-20 17:35:01 -07:00
David Harris
f9ca280e01 continued cleanup 2023-04-20 16:48:23 -07:00
David Harris
ea7c50e0ee Reordered fdivsqrtpreproc to follow logic 2023-04-20 16:38:47 -07:00
David Harris
ca0269c094 Started fdivsqrtpreproc flow organization 2023-04-20 16:25:19 -07:00
David Harris
c431278fe6 Fmv h/q comments in controller 2023-04-20 16:24:58 -07:00
David Harris
94d1533264
Merge pull request #256 from cturek/main 
Simplifying fds to follow diagram
 2023-04-20 16:07:22 -07:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main 
removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
 2023-04-19 14:49:50 -07:00
Sydeny
b76ed145e6 removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% 2023-04-19 13:30:12 -07:00
Alec Vercruysse
7ba2bfd4b6 CacheFSM logic simplification for AMO operations 
Ran this by Ross.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Cedar Turek
30bd1e2a33 created fdivsqrtcycles, moved cycles calculation from FSM to preproc 2023-04-18 16:14:45 -07:00
Cedar Turek
871d495ca1 gave integer bits to D instead of adding manually everywhere 2023-04-18 15:41:04 -07:00
Cedar Turek
054c8d638c moved D flop to preproc 2023-04-18 15:14:17 -07:00
Sydeny
4748fa0f6b Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-17 13:51:16 -07:00
David Harris
bdd5f5e611
Merge pull request #251 from masonadams25/main 
Removed redundent expression to increase coverage
 2023-04-17 12:37:27 -07:00
Mason Adams
4468086e06
Removed redundent expression to increase coverage 2023-04-17 14:13:26 -05:00
David Harris
b00b8ba366 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Diego Herrera Vicioso
34dd481f93 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Sydeny
af51b6f16c trimming comments on fctrl bug fixes 2023-04-15 00:48:32 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
Limnanthes Serafini
5952a4b0a3 Final small fix 2023-04-14 14:15:52 -07:00
Limnanthes Serafini
34aedc4f79 indent fix 2023-04-14 14:14:34 -07:00
Limnanthes Serafini
95223bf11c More cleanup 2023-04-13 21:34:50 -07:00
Limnanthes Serafini
28dd41291a More cleanup 2023-04-13 21:02:30 -07:00
Limnanthes Serafini
94b686fcf6 More changes 2023-04-13 21:02:15 -07:00
Limnanthes Serafini
5d12afa671 Some cleanup 2023-04-13 21:01:57 -07:00
David Harris
cfca584bc7 Merged coverage-exclusions 2023-04-13 18:15:23 -07:00
David Harris
b378001213
Merge pull request #237 from SydRiley/main 
fctrl coverage at 100% after removing redundancies from conditionals
 2023-04-13 17:10:46 -07:00
Limnanthes Serafini
e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
c427b4c896 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
David Harris
8db317133c Starting fdivsqrt cleanup 2023-04-13 16:53:33 -07:00
Sydeny
1dab409bae Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Alec Vercruysse
a52eb01407 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
a3d9e11b0f cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
Alec Vercruysse
800f0245f3 Cachefsm gate LRUWriteEn with ~FlushStage 2023-04-12 13:32:36 -07:00
Sydeny
e2520c8a27 fctrl coverage at 100% after removing redundancies from conditional statements 2023-04-12 13:07:30 -07:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
e303d99d5b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
David Harris
44023e7ee7 Removed unnecessary start term from initialization muxes to simplify and improve coverage 2023-04-12 03:34:01 -07:00
David Harris
28c02a7e6a Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
d60e3aaf53 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
729f81a0df refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
1ce2ab5daa Coverage and readability improvements to LRUUpdate logic 
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
214abc7006 Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b Remove FlushStage Logic from CacheLRU 
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
3fc6bb0c40 Exclude (FlushStage & SetValidWay) condition for RO caches 
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
 2023-04-12 01:15:35 -07:00
Limnanthes Serafini
fdb81e44c9 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Alexa Wright
34fd402f23 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
Ross Thompson
132016f131 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
Kevin Thomas
640310cf94 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
David Harris
4a2f641348 Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
495f2ed274 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
David Harris
5119222c2f Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
7ad8d7f774 Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
c24e81c57f Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Ross Thompson
fe922c8fac Fixed syntax error. 2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1 Added note about strange vivado behavior not inferring block ram. 2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997 Similifed the no byte write enabled version of the sram model. 2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-06 12:38:41 -05:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main 
Fixes the issue introduced by the fix for issue 203
 2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf Fixed wally64/32priv test hangup. 
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
 2023-04-05 23:13:45 -05:00
Kevin Thomas
e70a081924 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 17:43:43 -05:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
Alec Vercruysse
2a3d9f8c89 Update ram1p1rwe (ce & we) coverage exlusion explanation 2023-04-05 14:54:58 -07:00