Ross Thompson
2d7749db7f
Updated globalhistory predictor.
2023-02-09 14:48:02 -06:00
Ross Thompson
cce9388d4a
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-09 14:28:20 -06:00
Ross Thompson
ca3aef3388
Merge branch 'main' of github.com:ross144/cvw
2023-02-08 18:25:16 -06:00
Ross Thompson
962c018991
Simplified branch predictor.
2023-02-08 18:24:38 -06:00
David Harris
e6b6b82ad1
Merge pull request #73 from mmasserfrye/main
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corrected feature (elimination) sweep, changed default freqs, plotting
2023-02-07 16:44:20 -08:00
David Harris
1cfd68b0e3
Merge pull request #72 from ross144/main
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Fixed a preformance bug in the branch predictor.
2023-02-07 16:43:29 -08:00
David Harris
f41a8f9e62
Update README.md
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gcc seems to have changed its path to executables
2023-02-07 16:35:44 -08:00
Ross Thompson
ff7dc4f34a
fpga constraints updates
2023-02-07 15:22:14 -06:00
Madeleine Masser-Frye
49bf56b939
Merge branch 'openhwgroup:main' into main
2023-02-07 23:20:41 +02:00
Madeleine Masser-Frye
0cbf50ed80
changed default freqs for synth sweeps
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updated plotting to not overlap labels
2023-02-07 21:18:39 +00:00
Ross Thompson
834e9f1903
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-07 14:37:51 -06:00
Madeleine Masser-Frye
b9f05c02e3
for feature sweep
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now adding feature modifications on top of each other
2023-02-07 20:07:43 +00:00
Ross Thompson
0678f3f2b7
Branch predictor cleanup.
2023-02-07 14:01:59 -06:00
David Harris
00a8644b23
Merge pull request #69 from ross144/main
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Fixed spilled instruction fetch ITLB miss interlock with load miss.
2023-02-06 15:37:02 -08:00
Ross Thompson
c33230d1c1
Fixed Bug 66.
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If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish.
2023-02-06 17:32:28 -06:00
David Harris
5ce7189c33
Merge pull request #68 from ross144/main
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Found a minor bug in hptw. hptw fsm had unreachable state.
2023-02-06 14:51:38 -08:00
Ross Thompson
4e8ef4a0ac
Removed unreachable if branch in hptw next state logic.
2023-02-06 16:42:07 -06:00
Ross Thompson
70e96a7531
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-06 16:35:20 -06:00
Ross Thompson
a07684914b
Updated imperas git repo to use a different hash.
2023-02-06 16:35:03 -06:00
Ross Thompson
d1cdbdd8df
Merge branch 'main' of github.com:ross144/cvw
2023-02-06 16:34:28 -06:00
David Harris
711ed99b3b
Merge pull request #67 from eroom1966/main
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Add RVVI Address size to configure MMU operations
2023-02-06 08:01:28 -08:00
eroom1966
ae3ac02556
remove dead code for ignoring fflags/fcsr
2023-02-06 15:53:29 +00:00
eroom1966
d88b56eebc
remove leading space
2023-02-06 14:01:05 +00:00
eroom1966
232bfbcfd0
remerge changes
2023-02-06 13:43:12 +00:00
David Harris
69e9c85d7a
Merge pull request #63 from davidharrishmc/dev
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Cleanup
2023-02-04 20:15:12 -08:00
David Harris
077edbf78d
changed USE_SRAM to modify wally-config rather than wally-shared
2023-02-04 20:13:24 -08:00
David Harris
7cf98811f3
Parenthesized reduction operators to avoid DC lint
2023-02-04 18:49:47 -08:00
David Harris
66fa1e67bb
Removed redundant USE_SRAM from wally-shared.vh (already in wally-config.vh)
2023-02-04 18:49:25 -08:00
David Harris
2303da01a8
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-02-04 18:32:31 -08:00
David Harris
4091418f00
Merge pull request #64 from mmasserfrye/main
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Now modifying dtim and irom even when USESRAM=1
2023-02-04 18:11:39 -08:00
Madeleine Masser-Frye
9454eb921d
Now modifying dtim and irom even when USESRAM=1
2023-02-05 00:02:50 +00:00
David Harris
6abd5dd644
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-02-04 09:59:44 -08:00
David Harris
5256d3a625
More progress on debug.S, but it crashes in Spike
2023-02-04 09:59:22 -08:00
Ross Thompson
4fed1d5e3d
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-04 11:28:26 -06:00
Ross Thompson
d7a65b2576
Updates to imperas test bench.
2023-02-04 11:28:23 -06:00
David Harris
43668a3fc5
Developing debug test
2023-02-04 08:31:47 -08:00
David Harris
b09002c71d
Fixed license on testbench files
2023-02-04 08:19:20 -08:00
David Harris
2c69adc5f7
Started making debug testcase
2023-02-04 08:18:55 -08:00
David Harris
ae54860805
Renamed wally-piplined.do to wally.do
2023-02-04 04:38:41 -08:00
David Harris
835f793db9
Merge pull request #62 from davidharrishmc/dev
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../synthDC/Makefile
2023-02-04 04:29:56 -08:00
David Harris
be08523ba0
Added license headers
2023-02-04 04:29:27 -08:00
David Harris
f89e642312
../synthDC/Makefile
2023-02-04 04:19:09 -08:00
David Harris
52e028fc7a
Merge pull request #53 from davidharrishmc/dev
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Removed pipelined hierarchy and renamed regression to sim
2023-02-04 04:15:02 -08:00
David Harris
6b9ae4fc89
Fixed merge issues on synthDC PR
2023-02-04 04:13:40 -08:00
David Harris
e831baf335
Improved illegal NaN-box detection and formatted fsgninj
2023-02-04 03:42:20 -08:00
David Harris
18750e0f0a
Merge pull request #61 from mmasserfrye/main
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USE_SRAM parameter, makefile config cleaning
2023-02-04 03:28:44 -08:00
Madeleine Masser-Frye
4be41ae25c
finishing the job of the last commit
2023-02-04 10:24:01 +00:00
Madeleine Masser-Frye
b78ce62748
added use sram parameter, cleaned up config writing, added single synth functionality to wallySynth
2023-02-04 09:50:36 +00:00
David Harris
fa276d67b4
Merge pull request #60 from ross144/main
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Optimized PCLink logic.
2023-02-03 16:42:27 -08:00
Ross Thompson
f5468ebd7a
Replaced PCLinkX registers with a +2/4 adder in the execution stage.
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David and I estimate this is lower hardware cost.
2023-02-03 18:19:47 -06:00
