12 Commits

Author	SHA1	Message	Date
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
Ross Thompson	1bb8d36308	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
Ross Thompson	ec44774c77	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	5cf686429d	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
Ross Thompson	fdc17f5017	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
Ross Thompson	000d713cb5	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
Ross Thompson	48c036a923	Oups. My hack for DivE interrupt prevention was wrong.	2022-01-12 14:17:16 -06:00
Ross Thompson	796316495d	Hack "fix" to prevent interrupt from occuring during an integer divide. ... This is not the desired solution but will allow continued debuging of linux.	2022-01-12 14:17:16 -06:00
Ross Thompson	55456e465c	Added icache access and icache miss to performance counters.	2022-01-09 22:56:56 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00