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Author SHA1 Message Date
Ross Thompson
51dfa16f59 Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
Ross Thompson
48c49802b2 Fixed linting issues. 2022-04-01 15:20:45 -05:00
Ross Thompson
301f20052b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-01 12:50:34 -05:00
Ross Thompson
19a8df9739 Added wave config 
added new signals to ILA.
 2022-04-01 12:44:14 -05:00
David Harris
61e1758a69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-01 16:49:18 +00:00
David Harris
c6960ede37 Changed Linux disassembly to -S to preserve source code lines 2022-04-01 16:49:13 +00:00
bbracker
9d26bfe71d expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00
bbracker
e09079d8b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 17:54:43 -07:00
bbracker
55df8bc3f7 fix lingering overrun error bug 2022-03-31 17:54:32 -07:00
Ross Thompson
48c862d536 Added PLIC to ILA. 2022-03-31 16:44:49 -05:00
Ross Thompson
da93d14050 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 16:30:55 -05:00
Ross Thompson
b5cdf035fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 15:50:04 -05:00
Ross Thompson
ade4a4cd5e Notes on what to change in ram.sv. 2022-03-31 15:48:15 -05:00
bbracker
bdb3417656 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 13:46:32 -07:00
bbracker
0f7e995055 simplify plic logic 2022-03-31 13:46:24 -07:00
David Harris
c7043e4d63 Added SystemVerilog flag to fma.do so that fma16 compiles properly 2022-03-31 17:00:38 +00:00
Ross Thompson
88c5cdc873 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:39:41 -05:00
Ross Thompson
bf9683f0d2 Forced to go back to hard coded preload. 2022-03-31 11:39:37 -05:00
Ross Thompson
54001222cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-31 11:38:55 -05:00
Ross Thompson
285fc6fd4d Modified clint to support all byte write sizes. 2022-03-31 11:31:52 -05:00
David Harris
dd3af17b3f Added synthesis script for fma16 2022-03-31 00:51:33 +00:00
David Harris
3457c6e512 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 23:06:36 +00:00
Ross Thompson
84a478c053 Updated constraints file. 2022-03-30 17:48:44 -05:00
Ross Thompson
471f204c48 Added bootrom.txt. 2022-03-30 17:29:48 -05:00
Ross Thompson
baf4d8875e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 17:28:30 -05:00
bbracker
69a0f6e00b big interrupts refactor 2022-03-30 13:22:41 -07:00
Ross Thompson
0a5b500aca Changed sram1p1rw to have the same type of bytewrite enables as bram. 2022-03-30 11:38:25 -05:00
David Harris
9b1f85d353 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:26:27 +00:00
David Harris
08fad856e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-03-30 16:13:42 +00:00
Ross Thompson
e4f4e1bd43 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-30 11:09:44 -05:00
Ross Thompson
f52ab01362 Partial cleanup of memories. 2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656 Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload. 2022-03-30 11:04:15 -05:00
Ross Thompson
997c1b87fe rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory. 2022-03-29 23:48:19 -05:00
Ross Thompson
66e9380cfb Partial fix to allow byte write enables with fpga and still get a preload to work. 2022-03-29 19:12:29 -05:00
Kip Macsai-Goren
d031c003ba fixed arch bge test signature output location after update 2022-03-29 20:45:18 +00:00
David Harris
03fa9084bc Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv 2022-03-29 19:16:41 +00:00
David Harris
c4f2c6b110 fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Kip Macsai-Goren
56a0542405 made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes 2022-03-29 02:26:42 +00:00
Kip Macsai-Goren
a6d90a25c2 fixed signature location of the new periph with no compressed instructions 2022-03-29 02:15:17 +00:00
bbracker
8ea25e591b fix typo that Madeleine found 2022-03-28 15:39:29 -07:00
Ross Thompson
c88541cf6b test. 2022-03-28 17:04:58 -05:00
bbracker
b88eaf250d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-28 13:41:14 -07:00
bbracker
a5c32898a0 checkpointSweep is bash-specific, so add shebang to make it so 2022-03-28 13:40:50 -07:00
Kip Macsai-Goren
709f8e6e0d fixed double multiplication on vectored interrupts 2022-03-28 19:12:31 +00:00
Kip Macsai-Goren
eb337fd3e1 added test config that doesn't use compressed instructions for privileged tests 2022-03-28 19:12:31 +00:00
Ross Thompson
09ff5c2c45 Updated debug2.xdc ila constraints to match rtl. 2022-03-28 10:52:26 -05:00
Ross Thompson
668eb828d6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-03-28 10:23:25 -05:00
Ross Thompson
5f88536730 Temporary change of plic uart id to 10. 2022-03-28 10:23:20 -05:00
bbracker
501dc7cd68 fix genCheckpoint.sh binary memory dump 2022-03-27 20:54:59 -07:00
bbracker
9b5bbd29b4 change genCheckpoint.sh to only log 128MB of RAM 2022-03-27 19:16:39 -07:00