10 Commits

Author	SHA1	Message	Date
David Harris	07f34c8263	.gitmodule added dirty riscv-arch-test	2021-12-29 23:50:17 +00:00
David Harris	e97e512da9	Started FIR test code and started incorporating Imperas tests	2021-12-25 22:39:51 +00:00
David Harris	434f49c03e	Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead	2021-12-21 02:35:41 +00:00
Kevin Kim	869cd44533	added arch-test submodule	2021-11-30 18:22:08 -08:00
Kevin Kim	6323609da9	Added git submodules ... -riscv-arch-test -rscv-isa-sim submodules are added in addins/ directory	2021-11-30 18:16:37 -08:00
kipmacsaigoren	b2677d2090	Added git things to make it all a little nicer and synthesis work.	2021-09-15 12:15:53 -05:00
Teo Ene	1d5d7a7840	Flow updated for 90nm	2021-07-01 13:32:42 -05:00
Teo Ene	bd99a5613a	sky130 18T and 15T cell libraries removed ... Upon noticing their size, concerns were raised about available drive space. As 12T is the main implementation focus, the decision was made to remove 15T and 18T. Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.	2021-02-14 09:05:41 -06:00
Teo Ene	af3a888cde	Removed riscv-o3 module	2021-02-12 16:08:34 -06:00
Teo Ene	a54070d074	Added synth and PnR flow	2021-01-25 14:28:14 -06:00