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3 Commits

Author SHA1 Message Date
Ross Thompson
c33230d1c1 Fixed Bug 66. 
If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish.
 2023-02-06 17:32:28 -06:00
Ross Thompson
4e8ef4a0ac Removed unreachable if branch in hptw next state logic. 2023-02-06 16:42:07 -06:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00