14 Commits

Author	SHA1	Message	Date
cturek	10c2d45888	div tests in sim-wally	2022-11-30 02:32:04 +00:00
David Harris	f2517f8290	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
Katherine Parry	7268b4b334	removed underflow from inexactct calculation	2022-07-18 17:51:18 +00:00
Katherine Parry	5cb9c9f319	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
David Harris	5612ca7041	qslc_r4a2 generator	2022-06-09 17:26:47 +00:00
Katherine Parry	eb93bd46d7	fma synth warnings and errors removed	2022-06-06 16:06:04 +00:00
Katherine Parry	5ae63f913a	fixed compilation errors	2022-06-03 15:34:17 +00:00
Katherine Parry	c264585fe8	single and double conversions pass all tests	2022-05-25 23:02:02 +00:00
Katherine Parry	6bc31f2e78	Fixed unpacker bug LT EQ LE pass testfloat	2022-05-20 17:19:50 +00:00
David Harris	23868a33bc	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	9e0055cbb9	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	b967bcede2	LSU Cleanup	2022-01-15 01:11:17 +00:00
Katherine Parry	631d05dcdc	some FPU test fixes	2022-01-06 23:03:20 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00