Katherine Parry
|
efdec72df1
|
Fixed writting MStatus FS bits
|
2021-07-13 13:20:30 -04:00 |
|
Katherine Parry
|
36f59f3c99
|
Almost all convert instructions pass Imperas tests
|
2021-07-11 18:06:33 -04:00 |
|
bbracker
|
d3dd70e3e6
|
more completely uncomment MMU tests to make sim wally work
|
2021-07-06 14:33:52 -04:00 |
|
Kip Macsai-Goren
|
20cd0e208b
|
added new mmu tests to makefrag and commented out in the testbench
|
2021-07-05 10:54:30 -04:00 |
|
David Harris
|
5f91b339aa
|
Added F_SUPPORTED flag to disable floating point unit when not in MISA
|
2021-07-05 10:30:46 -04:00 |
|
David Harris
|
9645b023c9
|
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
|
2021-07-04 01:19:38 -04:00 |
|
Katherine Parry
|
7e3483b283
|
FPU forwarding reworked pt.1
|
2021-06-24 18:39:18 -04:00 |
|
Katherine Parry
|
8eed89616c
|
fpu clean-up
|
2021-06-23 16:42:40 -04:00 |
|
Katherine Parry
|
353a27f12f
|
rv64f FLW passes imperas tests
|
2021-06-22 16:36:16 -04:00 |
|
David Harris
|
7930c2ebb4
|
Commented out 100k tests to improve speed
|
2021-06-21 01:43:18 -04:00 |
|
Katherine Parry
|
2b67f25683
|
all rv64f instructions except convert, divide, square root, and FLD pass
|
2021-06-20 20:24:09 -04:00 |
|
David Harris
|
35c74348a4
|
allow all size memory access in CLINT; added underscore to peripheral address symbols
|
2021-06-18 08:05:50 -04:00 |
|
David Harris
|
01d6ca1e2a
|
Fixed lint WIDTH errors
|
2021-06-09 20:58:20 -04:00 |
|
bbracker
|
cc91c774a6
|
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
|
2021-06-08 12:41:25 -04:00 |
|
bbracker
|
e7e4105931
|
* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
|
2021-06-08 12:32:46 -04:00 |
|
Kip Macsai-Goren
|
c96695b1b6
|
implemented simpler page mixers, cleaned up a bit
|
2021-06-07 18:32:34 -04:00 |
|
Katherine Parry
|
75a6097467
|
fixed lint warnings for fpu and lzd
|
2021-06-05 12:06:33 -04:00 |
|
Katherine Parry
|
fc65aedbd6
|
Double-precision FMA instructions
|
2021-06-04 14:00:11 -04:00 |
|
Kip Macsai-Goren
|
1ea9b94cf1
|
added tests for SV48 and translation off with vmem
|
2021-06-03 14:28:52 -04:00 |
|
James E. Stine
|
2eeb12c674
|
Updates to muldiv.sv for 32-bit div/rem
|
2021-06-01 15:31:07 -04:00 |
|
Ross Thompson
|
89ad4477e4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-06-01 11:33:12 -05:00 |
|
Ross Thompson
|
857f59ab5c
|
Now have global history working correctly.
|
2021-06-01 10:57:43 -05:00 |
|
James E. Stine
|
ddbdd0d5a2
|
Modify muldiv.sv to handle W instructions for 64-bits
|
2021-05-31 23:27:42 -04:00 |
|
bbracker
|
39ae743543
|
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
|
2021-05-28 23:11:37 -04:00 |
|
Katherine Parry
|
778ba6bbf5
|
classify unit created and passes imperas tests
|
2021-05-27 18:53:55 -04:00 |
|
Katherine Parry
|
1459d840ed
|
All compare instructions pass imperas tests
|
2021-05-27 15:23:28 -04:00 |
|
Katherine Parry
|
309e6c3dc1
|
FADD and FSUB imperas tests pass
|
2021-05-26 12:33:33 -04:00 |
|
Kip Macsai-Goren
|
8ae43a15d4
|
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
|
2021-05-24 20:59:26 -04:00 |
|
James E. Stine
|
295263e122
|
Mod for DIV/REM instruction and update to div.sv unit
|
2021-05-24 19:29:13 -05:00 |
|
Ross Thompson
|
c5310e85c1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-24 14:28:41 -05:00 |
|
Katherine Parry
|
90d5fdba04
|
FMV.X.D imperas test passes
|
2021-05-24 14:44:30 -04:00 |
|
Ross Thompson
|
8bf411c640
|
Updated branch predictor tests/benchmarks.
|
2021-05-24 11:13:33 -05:00 |
|
Katherine Parry
|
70968a4ec3
|
FSD and FLD imperas tests pass
|
2021-05-23 18:33:14 -04:00 |
|
bbracker
|
846553ac7d
|
improved PLIC test organization
|
2021-05-21 15:13:02 -04:00 |
|
James E. Stine
|
e70136ec78
|
Minor testbench updates to rv64icfd
|
2021-05-21 09:41:21 -05:00 |
|
James E. Stine
|
23769e36a5
|
Update to testbench-imperase for rv64icfd
|
2021-05-21 09:28:44 -05:00 |
|
James E. Stine
|
fed3b30557
|
Update to FLD/FSD testbench
|
2021-05-21 09:26:55 -05:00 |
|
James E. Stine
|
c89d3e01bb
|
Update to rv64icfd wally-config to run through FP tests
|
2021-05-21 09:22:17 -05:00 |
|
Katherine Parry
|
4db7f3065c
|
FMV.D.X imperas test passes
|
2021-05-20 22:18:33 -04:00 |
|
Katherine Parry
|
06af239e6c
|
FMV.D.X imperas test passes
|
2021-05-20 22:17:59 -04:00 |
|
bbracker
|
979a9bf037
|
commented out MSTATUS test
|
2021-05-19 12:38:01 -04:00 |
|
James E. Stine
|
44dc665fc5
|
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
|
2021-05-18 13:48:44 -05:00 |
|
David Harris
|
26531f2634
|
fixed rv64mmu makefile
|
2021-05-18 14:25:55 -04:00 |
|
Katherine Parry
|
9464c9022d
|
floating point infinite loop removed from imperas tests
|
2021-05-18 10:42:51 -04:00 |
|
James E. Stine
|
daf780b9c2
|
Mod Imperas Testbench for updated Div/Rem
|
2021-05-17 16:56:30 -05:00 |
|
Domenico Ottolia
|
88ab07d456
|
Forgot to add csr permission tests to testbench
|
2021-05-04 20:20:22 -04:00 |
|
ushakya22
|
682bc7b58e
|
Added mip tests to testbench
|
2021-05-04 15:36:06 -04:00 |
|
Domenico Ottolia
|
8398e653dd
|
Re-add medeleg tests to testbench
|
2021-05-04 14:42:20 -04:00 |
|
ushakya22
|
46f20745d7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-04 02:22:17 -04:00 |
|
ushakya22
|
b805b98a8c
|
Added MIE tests to testbench
|
2021-05-04 02:22:01 -04:00 |
|