49 Commits

Author	SHA1	Message	Date
David Harris	46680b80a7	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
Ross Thompson	51adf6cba9	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
David Harris	d72068d582	Only stall FPU to IEU on convert instructions with dependencies	2022-08-23 12:57:18 -07:00
David Harris	05aa18fe14	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
David Harris	d19fc99bf0	Simplify IEU-FP datapath	2022-08-23 11:16:36 -07:00
David Harris	0e489443f2	Finished FPU-LSU interface cleanup	2022-08-22 13:43:04 -07:00
David Harris	d556adde16	Simplified FPU-LSU interface to skip IEU	2022-08-22 13:28:51 -07:00
David Harris	2e20b3ed72	Removed 2-cycle FPU-IEU latency stall	2022-08-22 16:14:15 +00:00
David Harris	f6f09db4fb	Commented out unused comparators	2022-08-22 08:28:28 +00:00
Katherine Parry	8f98f3bfab	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
Madeleine Masser-Frye	6229779b97	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye	3c08861479	switched comparator to dc flip version	2022-06-21 20:30:33 +00:00
Katherine Parry	03d823f5d7	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
Katherine Parry	5f7072bd96	postprocessing unit created and passing all tests	2022-06-13 22:47:51 +00:00
David Harris	9065b684f8	Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit	2022-06-02 09:37:59 -07:00
David Harris	7cf5d481c0	Cleaned up comments in controller	2022-06-02 15:48:33 +00:00
David Harris	4335895b21	Added comments to some files, added a+b = 0 detector to comparator.sv	2022-05-28 09:41:48 +00:00
David Harris	61199ccd13	More signal cleanup	2022-05-12 15:39:44 +00:00
David Harris	7e764fbda1	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	e37d262e4c	PPA script progress	2022-05-11 18:11:51 +00:00
David Harris	554c2b3550	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
David Harris	9c4de0e9c1	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
David Harris	dee32f70bf	Switched to behavioral comparator for best PPA	2022-05-03 11:00:39 +00:00
David Harris	bc123b5564	Comparator experiments	2022-05-03 10:54:30 +00:00
David Harris	812b56acc6	Prefix comparator cleanup	2022-04-17 21:53:11 +00:00
David Harris	de5b61291f	Experiments with prefix comparator; minor fixes in WFI and testbench warnings	2022-04-17 21:43:12 +00:00
David Harris	aa1bac361d	Simplified SLT logic	2022-04-17 16:49:51 +00:00
Ross Thompson	58668812c1	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
David Harris	f314e60dc8	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
David Harris	01fa5c94bd	Register file comments about reset	2022-02-16 17:21:05 +00:00
David Harris	b537df2651	Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0	2022-02-12 05:50:34 +00:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
David Harris	0feb624bab	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
David Harris	0fbc32204c	cacheway cleanup	2022-02-03 16:07:55 +00:00
David Harris	c22f7eb11c	cacheway cleanup	2022-02-03 16:00:57 +00:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	5cf686429d	Merged in the debug ila updates.	2022-01-18 17:29:21 -06:00
David Harris	de7b9c127e	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	2df92af488	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
David Harris	27c1d73cb1	Code cleanup	2022-01-07 04:07:04 +00:00
David Harris	770780e394	Floating point test cleanup	2022-01-06 21:45:16 +00:00
David Harris	eff9cec415	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-06 18:10:32 +00:00
David Harris	aca26de498	FPU debug and configurable logic cleanup	2022-01-06 18:10:25 +00:00
Ross Thompson	9ea34e390a	Fixed xilinx synth error with $error in extend.sv	2022-01-05 17:48:08 -06:00
David Harris	6d4714651c	Removed more generate statements	2022-01-05 16:25:08 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00