Ross Thompson
27ef10df07
almost working icache.
2021-04-23 16:47:23 -05:00
Ross Thompson
020fb65adf
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
c42399bdb5
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Jarred Allen
5df6be3ad5
Add buildroot to regression test
2021-04-22 13:34:56 -04:00
Ross Thompson
d8ab7a5de2
Partially working icache.
...
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory. This keeps StallF high and
the icache FSM is never allowed to complete.
2021-04-22 10:20:36 -05:00
Ross Thompson
7b3735fc25
Fixed for the instruction spills.
2021-04-21 16:47:05 -05:00
Ross Thompson
532c8771ba
major progress.
...
It's running the icache is imperas tests now.
Compressed does not work yet.
2021-04-21 08:39:54 -05:00
Ross Thompson
f3093ac612
Why was the linter messed up?
...
There are a number of combo loops which need fixing outside the icache. They may be fixed in main.
We get to instruction address 50 now!
2021-04-20 22:06:12 -05:00
Ross Thompson
99424fb983
Progress on icache. Fixed some issues aligning the PC with instruction. Still broken.
2021-04-20 21:19:53 -05:00
Ross Thompson
251ece20fe
Broken icache. Design is done. Time to debug.
2021-04-20 19:55:49 -05:00
Jarred Allen
850f728cc7
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Noah Boorstin
6954e6df4c
buildroot: sim is now running!
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yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761
start to add buildroot testbench
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This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
368c94d4ff
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Jarred Allen
d99b8f772e
Merge from branch 'main'
2021-04-08 17:19:34 -04:00
bbracker
005f838b8d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 14:28:25 -04:00
bbracker
755e2e5771
merge testbench
2021-04-08 14:28:01 -04:00
David Harris
ac8a111d61
merge conflict resolution
2021-04-08 13:53:56 -04:00
David Harris
6a6ccca3c8
fixed sim-wally-32ic
2021-04-08 13:40:16 -04:00
bbracker
31c6b2d01f
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Ross Thompson
d21006d048
Partial fix to the integer divide stall issue.
2021-04-02 15:32:15 -05:00
James E. Stine
cff08adc3a
Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
2021-04-02 06:27:37 -05:00
James E. Stine
0495195d68
Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time.
2021-04-01 12:30:37 -05:00
Noah Boorstin
43532be770
busybear: clean up questa warnings
2021-03-31 14:02:15 -04:00
ushakya22
6b9ae41302
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 15:25:07 -04:00
Jarred Allen
631454ccf9
Merge branch 'cache2' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 13:32:33 -04:00
Jarred Allen
7ca57cc4fc
Merge branch 'main' into cache
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Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 12:55:01 -04:00
Noah Boorstin
b5a1691c2b
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/testbench/testbench-busybear.sv
2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb
Merge branch 'PPA' into main
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Conflicts:
wally-pipelined/testbench/testbench-privileged.sv
2021-03-25 20:35:21 -04:00
Jarred Allen
39bf2347bc
Fix error when reading an instruction that crosses a line boundary
2021-03-25 18:47:23 -04:00
ShreyaSanghai
139c2076a1
Removed PCW and InstrW from ifu
2021-03-26 01:53:19 +05:30
Noah Boorstin
05d362e334
regression: use busybear batch instead
2021-03-25 15:34:10 -04:00
Jarred Allen
3b4f0141f4
Begin work on compressed instructions
2021-03-25 14:43:10 -04:00
Domenico Ottolia
f134b09a97
Fix bugs with privileged tests
2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5
busybear: stop NOPing out atomics
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and bump regression to check for 800k instrs, up from 200k
2021-03-25 13:29:56 -04:00
Jarred Allen
0290568a52
Make cache output NOP after a reset
2021-03-25 13:18:30 -04:00
Jarred Allen
602271ff7b
rv64i linear control flow now working
2021-03-25 13:02:26 -04:00
Jarred Allen
4410944049
Merge branch 'main' into cache
2021-03-23 23:35:36 -04:00
Noah Boorstin
69e5319675
busybear: more progress
2021-03-23 14:49:30 -04:00
Jarred Allen
0d05c51af9
Remove deleted signal from waves
2021-03-23 14:17:17 -04:00
Jarred Allen
7da8af4c68
Another tweak to regression-wally.py comments
2021-03-23 00:18:38 -04:00
Jarred Allen
82de84469f
Slight change to regression-wally.py comments
2021-03-23 00:02:40 -04:00
Noah Boorstin
d5bd5fa9d7
start migrating busybear over to InstrRawD/PCD
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this breaks busybear for now
2021-03-22 23:45:04 -04:00
Jarred Allen
3f897bbf53
Merge branch 'main' into cache
2021-03-22 14:50:22 -04:00
Noah Boorstin
74bcd9b994
regression: expect 200k instead of 100k busybear instrs
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and a minor busybear bugfix
2021-03-22 14:47:52 -04:00
Jarred Allen
5b1db9b6a2
Change busybear testbench to reflect new location of InstrF
2021-03-20 18:20:27 -04:00
Jarred Allen
b63bfc7afa
Fix conflicts in ahb-waves that snuck through manual merging
2021-03-20 17:16:50 -04:00
Jarred Allen
279c09b27c
Merge changes from main
2021-03-18 18:58:10 -04:00
Jarred Allen
2a29def21c
Add icache's read request to ahb wavs
2021-03-18 18:52:03 -04:00
bbracker
85363e941d
AHB bugfixes and sim waveview refactoring
2021-03-18 18:25:12 -04:00
