15 Commits

Author	SHA1	Message	Date
Noah Boorstin	5902637632	buildroot: sim is now running! ... yes it only gets through 5 instructions right now. Yes that's my fault.	2021-04-17 14:44:32 -04:00
Domenico Ottolia	a149f2f3d8	Add support for vectored interrupts	2021-04-15 19:13:42 -04:00
Shreya Sanghai	75caa65df1	Cherry Pick merge of Shreya's localhistory predictor changes into main. ... fixed minor bugs in localHistory	2021-04-15 09:04:36 -05:00
Thomas Fleming	4b2765f8e2	Complete basic page table walker	2021-03-30 22:19:27 -04:00
bbracker	eea7e2e47e	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Shreya Sanghai	dfc86539cc	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	9386e6a524	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00
Noah Boorstin	847bf0b9a6	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	fa1407f6e3	everyone gets a bootram	2021-03-18 12:35:37 -04:00
Shreya Sanghai	d9b1e7d67f	added gshare and global history predictor	2021-03-16 17:03:01 -04:00
Shreya Sanghai	a79e26f9d8	added global history branch predictor	2021-03-16 16:06:40 -04:00
Shreya Sanghai	518618ad38	Merge branch 'counters' into main ... added a configurable number of performance counters	2021-03-16 11:01:30 -04:00
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Shreya Sanghai	7cd8f1a592	added performance counters	2021-03-04 11:42:52 -05:00
Brett Mathis	11e2666bb2	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00