Katherine Parry
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e7190b0690
|
renamed top level FPU wires
|
2021-05-25 20:04:34 -04:00 |
|
Kip Macsai-Goren
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33cd133a65
|
completed mstatus test for rv32p, rv64p, updated testbench to reflect
|
2021-05-25 15:44:52 -04:00 |
|
Kip Macsai-Goren
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45e7628e90
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-25 15:28:19 -04:00 |
|
Ross Thompson
|
fec40a1b75
|
fixed bug with icache miss spill fsm branch.
|
2021-05-25 14:26:22 -05:00 |
|
James E. Stine
|
bb5404e14a
|
Update FPregfile to use more compact code and better structure for ease in reading
|
2021-05-25 13:21:59 -05:00 |
|
Ross Thompson
|
063e458ff0
|
Merge remote-tracking branch 'refs/remotes/origin/main' into main
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2021-05-24 23:25:36 -05:00 |
|
Ross Thompson
|
16e037b8e9
|
Fixed bug in the two bit sat counter branch predictor. The SRAM needs to be read enabled by StallF.
|
2021-05-24 23:24:54 -05:00 |
|
Kip Macsai-Goren
|
8ae43a15d4
|
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
|
2021-05-24 20:59:26 -04:00 |
|
James E. Stine
|
c4f3f2f783
|
Minor cosmetic elements on div.sv
|
2021-05-24 19:30:28 -05:00 |
|
James E. Stine
|
295263e122
|
Mod for DIV/REM instruction and update to div.sv unit
|
2021-05-24 19:29:13 -05:00 |
|
bbracker
|
f755827c90
|
slightly more path independence for using verilator
|
2021-05-24 18:11:56 -04:00 |
|
bbracker
|
920dd7bd8d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-24 17:09:14 -04:00 |
|
bbracker
|
b4bc4b7ee2
|
peripheral testing standardization
|
2021-05-24 17:08:40 -04:00 |
|
Ross Thompson
|
c5310e85c1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-24 14:28:41 -05:00 |
|
Katherine Parry
|
90d5fdba04
|
FMV.X.D imperas test passes
|
2021-05-24 14:44:30 -04:00 |
|
Ross Thompson
|
65632cb7c9
|
Fixed minor bug in instruction class decoding.
|
2021-05-24 13:41:14 -05:00 |
|
Ross Thompson
|
72f77656a3
|
Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link).
|
2021-05-24 12:37:16 -05:00 |
|
Ross Thompson
|
8bf411c640
|
Updated branch predictor tests/benchmarks.
|
2021-05-24 11:13:33 -05:00 |
|
James E. Stine
|
6f38b7633c
|
Update header for FPadd
|
2021-05-24 08:28:16 -05:00 |
|
Katherine Parry
|
70968a4ec3
|
FSD and FLD imperas tests pass
|
2021-05-23 18:33:14 -04:00 |
|
bbracker
|
846553ac7d
|
improved PLIC test organization
|
2021-05-21 15:13:02 -04:00 |
|
James E. Stine
|
e70136ec78
|
Minor testbench updates to rv64icfd
|
2021-05-21 09:41:21 -05:00 |
|
James E. Stine
|
23769e36a5
|
Update to testbench-imperase for rv64icfd
|
2021-05-21 09:28:44 -05:00 |
|
James E. Stine
|
fed3b30557
|
Update to FLD/FSD testbench
|
2021-05-21 09:26:55 -05:00 |
|
James E. Stine
|
c89d3e01bb
|
Update to rv64icfd wally-config to run through FP tests
|
2021-05-21 09:22:17 -05:00 |
|
Katherine Parry
|
4db7f3065c
|
FMV.D.X imperas test passes
|
2021-05-20 22:18:33 -04:00 |
|
Katherine Parry
|
06af239e6c
|
FMV.D.X imperas test passes
|
2021-05-20 22:17:59 -04:00 |
|
bbracker
|
1d3db5ead5
|
small bit of busybear debug progress
|
2021-05-19 20:18:00 -04:00 |
|
bbracker
|
bf6337f2f7
|
plic implementation optimizations
|
2021-05-19 18:10:48 +00:00 |
|
bbracker
|
979a9bf037
|
commented out MSTATUS test
|
2021-05-19 12:38:01 -04:00 |
|
James E. Stine
|
304e70d3ae
|
Update rv64icfd batch script
|
2021-05-18 16:01:53 -05:00 |
|
James E. Stine
|
44dc665fc5
|
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
|
2021-05-18 13:48:44 -05:00 |
|
bbracker
|
e4d51ebef5
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-18 14:33:40 -04:00 |
|
bbracker
|
c495fc71f1
|
changed lint script to use absolute path for verilator because cron jobs stink at using paths
|
2021-05-18 14:33:22 -04:00 |
|
David Harris
|
26531f2634
|
fixed rv64mmu makefile
|
2021-05-18 14:25:55 -04:00 |
|
David Harris
|
5da159d17e
|
Removed rv64wally
|
2021-05-18 14:08:46 -04:00 |
|
David Harris
|
4d264c6f61
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
|
2021-05-18 14:01:19 -04:00 |
|
bbracker
|
a885d44129
|
commented changes to imperas makefiles
|
2021-05-18 13:34:48 -04:00 |
|
Katherine Parry
|
9464c9022d
|
floating point infinite loop removed from imperas tests
|
2021-05-18 10:42:51 -04:00 |
|
bbracker
|
2feb9309bb
|
script for running make and logging output
|
2021-05-17 22:12:18 -04:00 |
|
bbracker
|
02966dd649
|
changed makefiles so that make stops at bad source code that does not compile
|
2021-05-17 21:20:30 -04:00 |
|
bbracker
|
f00eb22700
|
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
|
2021-05-17 19:25:54 -04:00 |
|
bbracker
|
e4c90f503a
|
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
|
2021-05-17 18:44:47 -04:00 |
|
David Harris
|
9901f54b15
|
Deleted vish_stacktrace
|
2021-05-17 18:39:01 -04:00 |
|
David Harris
|
4370699f3d
|
Started MSTATUS tests
|
2021-05-17 18:37:56 -04:00 |
|
James E. Stine
|
e808b06b82
|
Forgot initialization config for div - apologies
|
2021-05-17 17:12:27 -05:00 |
|
Elizabeth Hedenberg
|
b818ce608a
|
commit ehedenberg coremark
|
2021-05-17 18:02:35 -04:00 |
|
Elizabeth Hedenberg
|
752fefd870
|
coremark commit ehedenberg final
|
2021-05-17 18:02:34 -04:00 |
|
James E. Stine
|
5506efc115
|
Add 32/64-bit shifter for update to shifter block
|
2021-05-17 17:02:13 -05:00 |
|
James E. Stine
|
3d3e3434f6
|
Cleanup of regression
|
2021-05-17 16:58:15 -05:00 |
|