10 Commits

Author	SHA1	Message	Date
Ross Thompson	b79872180b	Actually fixed the bus width issue coming out of the cache. ... The root cause is the ahb bus width can be different from LLEN. If we switch the d-cache to outputing LLEN and on LLEN intervals, subword read needs to operate on LLEN as well. Then the cache always outputs LLEN data which may need to be muxed down into 2 or more subwords if ABHW is smaller than LLEN.	2022-10-12 11:33:10 -05:00
David Harris	fde4832642	Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing	2022-10-10 07:12:37 -07:00
Ross Thompson	38e114a6c0	Fixed subword read to work with bigendian.	2022-09-15 14:08:04 -05:00
Ross Thompson	c7d3580637	Renamed signals in the LSU.	2022-09-13 11:47:39 -05:00
Katherine Parry	8f98f3bfab	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
Katherine Parry	03d823f5d7	added fld in rv32 - needs testing	2022-06-20 22:53:13 +00:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	2df92af488	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
David Harris	d66f7c841b	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00