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6,075 Commits 4 Branches 2 Tags 52 MiB
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13 Commits

Author SHA1 Message Date
eroom1966
1a10e48ecf update to allow running of ImperasDV with linux boot 
optimize performance of the tracer
 2023-03-27 09:46:16 +01:00
eroom1966
259fbc8d77 support linux 2023-03-22 17:10:32 +00:00
eroom1966
9ddfe52c9f Fix MISA RO and UART addresses 
It appears on inspection that the MISA register is read only in Wally
In which case this has now also been set in the ImperasDV representation
Also the Addresss for the UART R/W privileges are corrected
 2023-03-13 11:07:19 +00:00
eroom1966
0233130d9c Enhancements to support the PMA ranges 2023-03-10 14:09:22 +00:00
eroom1966
39ac3cd18f Add support for setting PMP registers 
Add support for async DV
 2023-03-08 12:44:53 +00:00
eroom1966
fe4d9d3e37 fix the memory map privileges in the REF model view 2023-03-02 15:25:27 +00:00
eroom1966
f86a12f282 update testbench for memory privileges 
also update configuration to define value of mimpid
 2023-03-01 15:37:11 +00:00
eroom1966
237a115377 add files to support coverage 2023-02-15 11:13:50 +00:00
Ross Thompson
70e96a7531 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-06 16:35:20 -06:00
eroom1966
d88b56eebc remove leading space 2023-02-06 14:01:05 +00:00
eroom1966
232bfbcfd0 remerge changes 2023-02-06 13:43:12 +00:00
Ross Thompson
4fed1d5e3d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-04 11:28:26 -06:00
David Harris
80f42a8638 Renamed regression to sim 2023-02-02 14:48:23 -08:00