Commit Graph

2 Commits

Author SHA1 Message Date
Ross Thompson
7a4218788c Imperas found a real bug in virtual memory.
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
Ross Thompson
2d8b0aa650 Modified makefiles to generate function address to name mappings for modelsim. 2022-02-01 18:25:03 -06:00