Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
026570d3da
Added new submodule for digilent fpga boards.
2023-07-17 16:25:37 -05:00
Victor Clements
9461b9db7e
pulling in FreeRTOS/kernel Submodule
2023-06-13 10:41:18 -07:00
Ross Thompson
f067935eed
Added Yujun Lin's branch predictor simulator. This is a C baseline module for common branch predictor algorithms.
2023-03-07 10:49:59 -06:00
Daniel Torres
16e4260dda
fixed gitmodules
2022-07-21 10:15:13 -07:00
Daniel Torres
e46e96e080
changed the default branch of embench
2022-07-21 10:14:05 -07:00
David Harris
e22d6a2f9a
Removed Sky130 libraries
2022-07-06 13:50:11 +00:00
DTowersM
12f465ea05
added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo
2022-06-13 23:33:10 +00:00
DTowersM
39ed36d0ba
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
2022-06-13 23:23:57 +00:00
James Stine
b9480a4643
Added the 12T submodule to the project.
2022-02-03 19:26:41 -06:00
David Harris
069f270d1a
Removed soc_flow
2022-01-31 22:58:33 +00:00
David Harris
c367d19fc6
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-31 00:59:49 +00:00
David Harris
ea85e185f1
gitmodules
2022-01-31 00:59:44 +00:00
James Stine
ef811c7786
Remove book_flow to add back later - will add synthDC back within 30m
2022-01-28 08:18:30 -06:00
David Harris
384cd0d092
Added synthesis submodules
2022-01-27 14:31:34 +00:00
David Harris
de7b9c127e
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
e25760d8e5
Added C test cases
2022-01-11 21:01:48 +00:00
David Harris
07f34c8263
.gitmodule added dirty riscv-arch-test
2021-12-29 23:50:17 +00:00
David Harris
e97e512da9
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
434f49c03e
Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead
2021-12-21 02:35:41 +00:00
Kevin Kim
869cd44533
added arch-test submodule
2021-11-30 18:22:08 -08:00
Kevin Kim
6323609da9
Added git submodules
...
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
2021-11-30 18:16:37 -08:00
kipmacsaigoren
b2677d2090
Added git things to make it all a little nicer and synthesis work.
2021-09-15 12:15:53 -05:00
Teo Ene
1d5d7a7840
Flow updated for 90nm
2021-07-01 13:32:42 -05:00
Teo Ene
bd99a5613a
sky130 18T and 15T cell libraries removed
...
Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
Teo Ene
af3a888cde
Removed riscv-o3 module
2021-02-12 16:08:34 -06:00
Teo Ene
a54070d074
Added synth and PnR flow
2021-01-25 14:28:14 -06:00
