32 Commits

Author	SHA1	Message	Date
Ross Thompson	839bede656	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
Ross Thompson	997c1b87fe	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
Ross Thompson	66e9380cfb	Partial fix to allow byte write enables with fpga and still get a preload to work.	2022-03-29 19:12:29 -05:00
Ross Thompson	7a25d577ba	Added new asserts to testbench.	2022-03-11 15:41:53 -06:00
bbracker	79ff8d3c80	remove imperas32p tests	2022-03-04 00:06:18 +00:00
bbracker	4fe35aadf2	add rv32a tests to regression	2022-03-02 17:54:55 +00:00
bbracker	29179c6787	add LRSC test and add wally64a to regression	2022-03-02 07:09:37 +00:00
bbracker	d8ddda760b	deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test	2022-03-01 00:37:46 +00:00
bbracker	202bd2f8f8	change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests	2022-02-22 03:46:08 +00:00
David Harris	f00b3ac27e	Fixed TIM tests; rv32e test still failing	2022-02-08 15:24:37 +00:00
David Harris	76dccbad91	Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail	2022-02-08 12:40:02 +00:00
David Harris	c61cd55c5c	Merged TIM and regular testbenches. RV32e now working and back in regression.	2022-02-08 12:18:13 +00:00
David Harris	72bc64ef28	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	2c67f32b97	RV32e tests	2022-02-04 14:30:36 +00:00
David Harris	a6708ed887	cache cleanup	2022-02-03 15:36:11 +00:00
David Harris	38bbe23d14	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	f4a553fd7d	Fixed testbench so coremark stops.	2022-02-02 11:37:48 -06:00
Ross Thompson	4b4cee3ddd	Added correct stop condition for coremark.	2022-02-02 09:53:51 -06:00
Ross Thompson	5407b72af9	Setup the main regression test to be able to handle coremark.	2022-02-01 17:00:11 -06:00
David Harris	7f91170bab	Comments in LSU code about restructuring	2022-01-27 15:53:59 +00:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
David Harris	b63e53bbdb	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
David Harris	6febce0001	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
David Harris	2bf4676ff8	LSU cleanup	2022-01-14 23:55:27 +00:00
Ross Thompson	aad28366d7	Partial local dtim in lsu configuration.	2022-01-13 17:50:31 -06:00
David Harris	bea6d0856d	Testbench directory cleanup	2022-01-07 17:02:16 +00:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	85fa620cfb	Finished removing generate statements	2022-01-05 16:41:17 +00:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	08e6a10480	Removed imperas mmu tests; using wallypriv instead	2022-01-04 23:14:53 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00