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Author	SHA1	Message	Date
David Harris	2180df4477	Removed assign statement inside always block	2023-11-13 07:23:15 -08:00
David Harris	0647142ffa	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-13 05:34:14 -08:00
David Harris	a570199ad5	Merge pull request #469 from stineje/main ... update ppaAnalyze to analyze correctionly freqSweep	2023-11-13 05:33:37 -08:00
James E. Stine	964b5f9c50	update ppaAnalyze to analyze correctionly freqSweep	2023-11-13 02:39:25 -06:00
David Harris	5e14f7c422	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-12 20:24:25 -08:00
David Harris	ee4f752d3c	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:27 -08:00
David Harris	24942f9054	DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst	2023-11-12 20:23:14 -08:00
Rose Thompson	40e69b82da	Merge pull request #468 from davidharrishmc/dev ... Divider optimization	2023-11-12 20:05:44 -08:00
David Harris	75216f8b2a	Divider cleanup	2023-11-12 19:41:12 -08:00
David Harris	b49330c556	Explained sqrt preshifting	2023-11-12 10:05:54 -08:00
David Harris	fdda3d6cde	Renamed qsel to uslc and simplified radix2 uslc	2023-11-12 06:36:57 -08:00
David Harris	65c5ec6e9d	fdivsqrt comment improvements	2023-11-12 06:15:47 -08:00
Rose Thompson	b0dcfddfb1	Merge pull request #467 from davidharrishmc/main ... Sanity in FDIVSQRT bit counts	2023-11-11 16:37:25 -08:00
David Harris	ac1051f67b	Cleaned up number of bits in fdivsqrt	2023-11-11 15:50:06 -08:00
David Harris	051286e703	Bug fixes related to size of fpdivsqrt bit count and number of cycles	2023-11-11 05:58:53 -08:00
David Harris	a3ca197a70	Fixed testbench-fp to reflect signal name changes	2023-11-11 04:05:34 -08:00
Rose Thompson	ec9fbee7db	Merge pull request #466 from stineje/main ... Add pap runs for sweep	2023-11-10 22:25:55 -08:00
Rose Thompson	bbfc8ad4a3	Merge pull request #465 from davidharrishmc/dev ... fdivsqrt cleanup	2023-11-10 22:25:09 -08:00
James E. Stine	4a6b2b0299	Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH	2023-11-10 21:10:35 -06:00
James E. Stine	1af093b368	Update ppa/ppaSynth.py for sky130 and better sweep parameterization	2023-11-10 21:07:36 -06:00
James E. Stine	48c1e19247	Add bestSynths.csv that are the initial values. If this is re-run after ppaAnalysis.py is run, more refinement can be made	2023-11-10 21:06:24 -06:00
James E. Stine	26db31cfde	update README for ppaSynth.py	2023-11-10 21:05:42 -06:00
David Harris	35efb7082c	fdivsqrt parameter cleanup	2023-11-10 18:33:08 -08:00
David Harris	6ed5ba4a85	Simplified out LOGRK parameter	2023-11-10 18:19:41 -08:00
David Harris	1302a89baf	divider cleanup	2023-11-10 18:01:13 -08:00
David Harris	d92f3e0216	fdivsqrt cleanup	2023-11-10 16:42:32 -08:00
David Harris	fbd6fce1ce	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-11-10 16:40:54 -08:00
Rose Thompson	534538b216	Simplification.	2023-11-10 18:39:36 -06:00
Rose Thompson	7158aa8390	Yay! Zicclsm passes my regression test now.	2023-11-10 18:28:51 -06:00
Rose Thompson	c29ef1666b	Found another bug in the RTL's Zicclsm alignment.	2023-11-10 18:26:55 -06:00
Rose Thompson	fa6e53d8cf	Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.	2023-11-10 17:58:42 -06:00
Rose Thompson	2491ef0e23	Fixed some more bugs in the Zicclsm signature.	2023-11-10 17:36:10 -06:00
Rose Thompson	3245e2a99e	Fixed bug in the Zicclsm test.	2023-11-10 17:34:23 -06:00
Rose Thompson	bd9a750583	Fixed spill bugs in the aligner.	2023-11-10 17:18:45 -06:00
Rose Thompson	b555620ac8	Fixed bug in the misaligned access test.	2023-11-10 17:02:15 -06:00
David Harris	f539f6171b	Simplified integer postnormalization shift	2023-11-10 14:55:36 -08:00
David Harris	72ad1d361c	Simplified IntDivNormShift	2023-11-10 14:28:57 -08:00
Rose Thompson	4b24878053	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
Rose Thompson	329f4456b0	Missed tests.vh.	2023-11-10 16:10:10 -06:00
Rose Thompson	89bf1a5cf9	Fixed bug which broke the non Zicclsm configs.	2023-11-10 16:08:04 -06:00
David Harris	b8bdb1c7d1	Simplified cycle count logic	2023-11-10 14:00:27 -08:00
David Harris	083ed09f1e	Reduced duplicated logic in fdivsqrtcycles	2023-11-10 11:25:54 -08:00
David Harris	4d77f28a19	Divsqrt cleanup: change Q to U, commenting code	2023-11-10 11:21:02 -08:00
David Harris	a1f94c9b0c	fdivsqrt parameter cleanup	2023-11-10 09:11:15 -08:00
Rose Thompson	5026772301	Merge pull request #463 from davidharrishmc/dev ... Dev	2023-11-10 08:48:07 -08:00
David Harris	fedf9c8a5a	Started cleaning up shifting leading 1 in fdivsqrt	2023-11-10 08:46:55 -08:00
David Harris	68115c6d6b	Imperas commenting	2023-11-10 08:26:32 -08:00
David Harris	ae769e90aa	Add Svadu support and SPI to imperas configuration	2023-11-10 06:27:25 -08:00
David Harris	5dbe869339	Merge pull request #460 from naichewa/main ... removed vestigial logic, added comments, deleted unused signals	2023-11-10 05:18:57 -08:00
naichewa	fd06472de8	Cleanup	2023-11-09 16:52:55 -08:00