Diego Herrera Vicioso
34dd481f93
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3
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Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Limnanthes Serafini
5952a4b0a3
Final small fix
2023-04-14 14:15:52 -07:00
Limnanthes Serafini
34aedc4f79
indent fix
2023-04-14 14:14:34 -07:00
Limnanthes Serafini
95223bf11c
More cleanup
2023-04-13 21:34:50 -07:00
Limnanthes Serafini
28dd41291a
More cleanup
2023-04-13 21:02:30 -07:00
Limnanthes Serafini
94b686fcf6
More changes
2023-04-13 21:02:15 -07:00
Limnanthes Serafini
5d12afa671
Some cleanup
2023-04-13 21:01:57 -07:00
David Harris
b378001213
Merge pull request #237 from SydRiley/main
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fctrl coverage at 100% after removing redundancies from conditionals
2023-04-13 17:10:46 -07:00
Limnanthes Serafini
e33721fbe4
Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim
2023-04-13 16:54:16 -07:00
Limnanthes Serafini
c427b4c896
Misc typo and indent fixing.
2023-04-13 16:54:15 -07:00
Sydeny
1dab409bae
Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu.
2023-04-13 16:27:53 -07:00
Alec Vercruysse
a52eb01407
Merge branch 'main' into coverage3
2023-04-12 16:00:15 -07:00
Alec Vercruysse
a3d9e11b0f
cachefsm exclude icache logic without code reuse
2023-04-12 15:57:45 -07:00
Alec Vercruysse
800f0245f3
Cachefsm gate LRUWriteEn with ~FlushStage
2023-04-12 13:32:36 -07:00
Sydeny
e2520c8a27
fctrl coverage at 100% after removing redundancies from conditional statements
2023-04-12 13:07:30 -07:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev
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Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
2023-04-12 12:21:03 -05:00
Alec Vercruysse
e303d99d5b
Merge branch 'main' into coverage3
2023-04-12 09:34:09 -07:00
David Harris
44023e7ee7
Removed unnecessary start term from initialization muxes to simplify and improve coverage
2023-04-12 03:34:01 -07:00
David Harris
28c02a7e6a
Fixed fdivsqrt to avoid going from done to busy without going through idle first
2023-04-12 02:48:40 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim
2023-04-12 01:34:45 -07:00
Alec Vercruysse
d60e3aaf53
only assign ClearDirtyWay for read-write caches
2023-04-12 01:15:35 -07:00
Alec Vercruysse
729f81a0df
refactor cachefsm to get full coverage
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I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
2023-04-12 01:15:35 -07:00
Alec Vercruysse
1ce2ab5daa
Coverage and readability improvements to LRUUpdate logic
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The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
214abc7006
Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE
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Some address options are only used in the D$ case.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b
Remove FlushStage Logic from CacheLRU
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For coverage.
LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.
Update cache.sv to reflect cacheLRU edit.
2023-04-12 01:15:35 -07:00
Alec Vercruysse
3fc6bb0c40
Exclude (FlushStage & SetValidWay) condition for RO caches
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Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.
I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
2023-04-12 01:15:35 -07:00
Limnanthes Serafini
fdb81e44c9
Minor logic cleanup (will elaborate in PR)
2023-04-11 19:29:39 -07:00
Alexa Wright
34fd402f23
Excluded coverage for misaligned instructions
2023-04-10 23:18:25 -07:00
Ross Thompson
132016f131
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-09 12:19:44 -05:00
Kevin Thomas
640310cf94
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-08 22:56:20 -05:00
David Harris
4a2f641348
Waived coverage on BTB memory with byte write enables tied high
2023-04-07 21:56:49 -07:00
David Harris
495f2ed274
Improved RAS predictor coverage by eliminating unreachable StallM term
2023-04-07 21:37:12 -07:00
David Harris
5119222c2f
Commented WFI non-flush in writeback stage of hazard unit
2023-04-07 21:27:13 -07:00
David Harris
7ad8d7f774
Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed
2023-04-07 20:43:28 -07:00
David Harris
c24e81c57f
Division cleanup
2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5
Simplified integer division preprocessing in fdivsqrt
2023-04-06 16:43:28 -07:00
David Harris
1569bfbb98
Removed redundant stall signal to get spill coverage
2023-04-06 14:07:50 -07:00
Ross Thompson
fe922c8fac
Fixed syntax error.
2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1
Added note about strange vivado behavior not inferring block ram.
2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997
Similifed the no byte write enabled version of the sram model.
2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-06 12:38:41 -05:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main
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Fixes the issue introduced by the fix for issue 203
2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf
Fixed wally64/32priv test hangup.
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The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
2023-04-05 23:13:45 -05:00
Kevin Thomas
e70a081924
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 17:43:43 -05:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2
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i$ coverage improvements
2023-04-05 17:29:35 -05:00
Alec Vercruysse
2a3d9f8c89
Update ram1p1rwe (ce & we) coverage exlusion explanation
2023-04-05 14:54:58 -07:00
Kevin Thomas
c4a9bb4269
Formating white space
2023-04-05 15:30:55 -05:00
Kevin Thomas
7345927cb1
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-05 15:04:12 -05:00
