15 Commits

Author	SHA1	Message	Date
Ross Thompson	e17de4eb11	Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. ... This solves the committedM issue.	2021-07-14 15:00:33 -05:00
Ross Thompson	d85bf23af3	Merged several of the load/store/instruction access faults inside the mmu. ... Still need to figure out what is wrong with the generation of load page fault when dtlb hit.	2021-07-06 13:43:53 -05:00
bbracker	7a652139b5	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
David Harris	9dd3857c26	Fixed lint WIDTH errors	2021-06-09 20:58:20 -04:00
bbracker	5026a42fac	* GPIO comprehensive testing ... * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr	2021-06-08 12:32:46 -04:00
bbracker	28abd28b1f	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
Domenico Ottolia	830787e3e1	Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts	2021-04-29 20:42:14 -04:00
ushakya22	de23edcfb9	fix to pcm bug	2021-04-29 15:21:08 -04:00
Thomas Fleming	5bff582608	Write PCM to TVAL registers	2021-04-22 16:17:57 -04:00
Domenico Ottolia	b1cd107a00	Add tests for scause and ucause	2021-04-15 19:41:25 -04:00
Domenico Ottolia	a149f2f3d8	Add support for vectored interrupts	2021-04-15 19:13:42 -04:00
bbracker	ccff1e6c99	rv64 interrupt servicing	2021-04-14 10:19:42 -04:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00