17 Commits

Author	SHA1	Message	Date
David Harris	865d5ce0b1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
Katherine Parry	36f59f3c99	Almost all convert instructions pass Imperas tests	2021-07-11 18:06:33 -04:00
Katherine Parry	06af239e6c	FMV.D.X imperas test passes	2021-05-20 22:17:59 -04:00
bbracker	1d3db5ead5	small bit of busybear debug progress	2021-05-19 20:18:00 -04:00
Jarred Allen	ebd9c0ee29	Remove signal which no longer exists from default waves, so sim-wally works	2021-04-29 14:41:10 -04:00
Ross Thompson	8e5409af66	Icache integrated! ... Merge branch 'icache-almost-working' into main	2021-04-26 11:48:58 -05:00
bbracker	a3487a9e47	do script refactor	2021-04-24 09:32:09 -04:00
ushakya22	6b9ae41302	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
Jarred Allen	631454ccf9	Merge branch 'cache2' into cache ... Conflicts: wally-pipelined/testbench/testbench-imperas.sv	2021-03-30 13:32:33 -04:00
Jarred Allen	7ca57cc4fc	Merge branch 'main' into cache ... Conflicts: wally-pipelined/regression/wave-dos/ahb-waves.do wally-pipelined/src/ifu/ifu.sv wally-pipelined/testbench/testbench-busybear.sv wally-pipelined/testbench/testbench-imperas.sv	2021-03-30 12:55:01 -04:00
ShreyaSanghai	139c2076a1	Removed PCW and InstrW from ifu	2021-03-26 01:53:19 +05:30
Jarred Allen	0290568a52	Make cache output NOP after a reset	2021-03-25 13:18:30 -04:00
Jarred Allen	602271ff7b	rv64i linear control flow now working	2021-03-25 13:02:26 -04:00
Jarred Allen	0d05c51af9	Remove deleted signal from waves	2021-03-23 14:17:17 -04:00
Jarred Allen	279c09b27c	Merge changes from main	2021-03-18 18:58:10 -04:00
bbracker	85363e941d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	98e93a63c0	maybe AHB works now	2021-03-18 17:47:00 -04:00