Ross Thompson
17636b3293
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
2021-06-25 11:05:17 -05:00
Kip Macsai-Goren
1485d29dde
Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
2021-06-24 20:01:11 -04:00
Kip Macsai-Goren
389b9a510e
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
bbracker
ced5039776
Revert "fixed forwarding"
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This reverts commit 0f4a4a6ade
2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade
fixed forwarding
2021-06-24 11:20:21 -04:00
Kip Macsai-Goren
547bf1d0af
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
abe5bc90bf
Partial addition of page table walker arbiter.
2021-06-23 17:03:54 -05:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
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Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
David Harris
1972d83002
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
