137 Commits

Author	SHA1	Message	Date
David Harris	10dfefa8ad	Simplified FWriteInt interfaces by merging into RegWrite	2021-12-18 05:36:32 -08:00
David Harris	bb49ba94a0	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-08 13:48:49 -08:00
Noah Limpert	5f0521d497	updated fcmp.sv instantiation to remove x*'s	2021-12-08 13:34:33 -08:00
David Harris	e14eb9872e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-08 12:33:59 -08:00
David Harris	d936342c97	Refactoring ALU and datapath muxes	2021-12-08 12:33:53 -08:00
Katherine Parry	80f026a734	FMA uses one LOA	2021-12-07 14:15:43 -08:00
Ross Thompson	5642918ead	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
David Harris	dda035891a	PIPELINE test running	2021-11-01 12:44:35 -07:00
David Harris	582c2bf37b	Fixed FResultSelM to select proper flags	2021-10-27 11:02:42 -07:00
David Harris	8287a1ef3e	Synchronous reset in non-flop blocks	2021-10-26 08:30:35 -07:00
David Harris	61fdb3d902	random lint cleanup	2021-10-23 11:24:36 -07:00
David Harris	8d9efcbafb	IEU cleanup	2021-10-23 11:13:28 -07:00
David Harris	d24bece3a8	Lint cleanup	2021-10-23 09:58:52 -07:00
David Harris	2e796e3da2	lint cleanup: FPU and privileged	2021-10-23 09:41:24 -07:00
David Harris	28d8f6d5cf	FMA and CSRC lint cleanup	2021-10-23 09:20:24 -07:00
David Harris	11b0607e63	Lint cleanup	2021-10-23 09:06:21 -07:00
David Harris	e2e950ac0f	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
David Harris	4c480a40f6	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-23 06:15:49 -07:00
David Harris	3249d65209	Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.	2021-10-23 06:15:26 -07:00
Ross Thompson	77e2b6f9a9	Merge branch 'main' into fpga	2021-10-22 16:09:16 -05:00
James E. Stine	f6e8e45901	Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking	2021-10-22 13:41:50 -05:00
Katherine Parry	7c7c0f538a	put the FMA priority encoders into their own module	2021-10-22 10:03:12 -07:00
James E. Stine	0dcca43f48	Get rid of lint warning - still need more testing though	2021-10-21 15:19:22 -05:00
James E. Stine	dd7dbaa382	Clean up some FPU and add pipelined fpdivsqrt to fpu.sv	2021-10-21 13:52:12 -05:00
James E. Stine	bafb3a983d	Fix fpdivsqrt lint error on CPA for convergence	2021-10-20 17:46:13 -05:00
Ross Thompson	de4ea16d32	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
James E. Stine	71b48048da	Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.	2021-10-20 12:00:41 -05:00
Katherine Parry	c34633804a	cvtfp module documented	2021-10-14 15:25:31 -07:00
James E. Stine	c5b99300e7	Clean up some signals - beautification onging	2021-10-14 17:12:00 -05:00
James E. Stine	1dba57dce7	Update to fpdivsqrt to go on posedge as it should. Also an update to ... individual regression test for TestFloat (still needs some tweaking)	2021-10-13 17:14:42 -05:00
Katherine Parry	b79021a73e	lint warnings fixed	2021-10-12 09:45:02 -07:00
Katherine Parry	539d21645f	some fpu lint warnings fixed - still working on it	2021-10-11 18:32:03 -07:00
Ross Thompson	f6c6cb9ed2	Merge branch 'main' into fpga	2021-10-11 18:17:58 -05:00
bbracker	90ccd60790	simplify flopenrc's that didn't actually need to be flopenrc's	2021-10-10 12:25:05 -07:00
Katherine Parry	77fe00947e	FMA matches diagram and lint warnings fixed	2021-10-09 17:38:10 -07:00
kipmacsaigoren	96565f9435	rename adder in fpu for synthesis	2021-10-08 17:47:54 -05:00
James E. Stine	a91c0c8fc7	Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat	2021-10-06 08:26:09 -05:00
Ross Thompson	a7be88a43b	Changes to make fpga synthesizable. ... Added preload to test simple program on wally in fpga.	2021-09-22 10:54:13 -05:00
David Harris	dd1e7548ed	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
Ross Thompson	570aab4275	Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.	2021-09-11 15:40:27 -05:00
Katherine Parry	70f332fe2f	FMA cleanup	2021-08-28 10:53:35 -04:00
Katherine Parry	c8847b27e8	all conversions go through the execute stage result mux	2021-08-16 13:06:09 -04:00
Katherine Parry	aedd71d570	move some FPU select muxs to execute stage	2021-08-13 14:41:22 -04:00
Katherine Parry	e00f181bcf	LZA added to FMA and attemting a merged FMA and adder in synthesis	2021-08-10 13:57:16 -04:00
Katherine Parry	d60e394ef9	all fpu units use the unpacking unit	2021-07-28 23:49:21 -04:00
Katherine Parry	30ac22edff	fixed some fpu lint errors	2021-07-24 16:41:12 -04:00
Katherine Parry	6c4aa624a5	fpu cleanup	2021-07-24 15:00:56 -04:00
Katherine Parry	ef28679721	fpu cleanup	2021-07-24 14:59:57 -04:00
David Harris	98660e0d19	Minor unpacking cleanup	2021-07-22 17:52:37 -04:00
David Harris	c9890afb7f	Move Z sign swapping out of unpacker	2021-07-22 14:32:38 -04:00