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117 Commits

Author SHA1 Message Date
David Harris
3906e706fd Removed integer from localparams 2023-01-27 14:40:06 -08:00
David Harris
5a81a26c9e Removed int/integer from parameters) 2023-01-27 14:27:04 -08:00
Ross Thompson
5494ee2159 Moved ebufsmarb into its own module. 2023-01-23 23:10:10 -06:00
Ross Thompson
a4d5ccc4d6 Added comments about needing move ebufsm into a new module. 2023-01-23 22:03:49 -06:00
Ross Thompson
626bcd8608 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
Ross Thompson
a6b14eb9ee Formatting. 2023-01-18 17:49:19 -06:00
Ross Thompson
0b244e289c Formating. 2023-01-18 17:30:08 -06:00
Ross Thompson
affca27ec4 Formatting 2023-01-18 17:14:37 -06:00
Ross Thompson
58a07399a2 Formatting 2023-01-18 17:03:45 -06:00
Ross Thompson
fc5424fa62 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
607c64e0ee Formating. 2023-01-18 16:52:46 -06:00
Ross Thompson
c34acab1d7 Formating. 2023-01-18 16:47:40 -06:00
Ross Thompson
a929e53576 More comments added to abhfsm. 2023-01-17 22:58:06 -06:00
Ross Thompson
4bfabc4136 formating ahbinterface. 2023-01-17 22:54:42 -06:00
Ross Thompson
4b47598138 Moved amoalu to lsu. 2023-01-17 22:45:46 -06:00
Ross Thompson
8f4f17a4c8 Added commenets and formating to abhcachefsm and abhcacheinterface. 2023-01-17 22:22:23 -06:00
Ross Thompson
f146a01344 Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
d6c80d937c Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
c75a164f46 Added comments to dtim and ahbcacheinterface. 2023-01-17 21:56:55 -06:00
David Harris
08fca1c517 ebu cleanup 2023-01-14 19:29:45 -08:00
David Harris
a6d8511a2e ebu cleanup 2023-01-14 19:19:34 -08:00
David Harris
91afe5522b generic cleanup 2023-01-14 19:02:38 -08:00
David Harris
8c6ddcc15b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
David Harris
3ea4dd4898 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
739c2c8322 Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
f541a277a8 Remove unused CACHE_ENABLED parameter 2023-01-07 09:57:24 -08:00
David Harris
d8f0425467 vclean working; started removing unused signals 2023-01-07 05:34:58 -08:00
Ross Thompson
3b791b768a Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
Ross Thompson
206bc7daa6 Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
41fe876e7a First pass at resolving ifu flush on trap rather than FlushD. 2022-12-22 15:53:06 -06:00
Ross Thompson
dacba855da Rough draft of cache flush fsm enhancement. 2022-12-16 15:28:22 -06:00
Ross Thompson
c50a2bd8bf Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
90697ef888 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
Ross Thompson
31d5eabd77 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
3653d6b3ed Renamed CACHE_EVICT to CACHE_WRITEBACK. 2022-11-09 17:43:06 -06:00
Ross Thompson
42c0a10d07 Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
Ross Thompson
2c80c2b35f Merged cacheable with seluncachedadr. 2022-10-17 13:29:21 -05:00
Ross Thompson
a0c5833d6d Fixed bug in EBU. 2022-10-05 14:51:12 -05:00
Ross Thompson
e6b36d0c02 Optimized the ebu's beat counting. 2022-10-05 10:58:23 -05:00
Ross Thompson
e6db1c5cf8 Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage. 2022-09-29 18:37:34 -05:00
Ross Thompson
47e936cab3 Renamed signals in EBU. 2022-09-29 18:29:38 -05:00
Ross Thompson
f9c4b32bd5 Simplification to EBU. 2022-09-29 18:06:34 -05:00
Ross Thompson
146ff6ff6a Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore. 2022-09-29 11:54:03 -05:00
Ross Thompson
638e506d0b Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
Ross Thompson
87485ed237 Possible fix for ifu/lsu arbiration issue. 2022-09-27 17:24:35 -05:00
Ross Thompson
afc6934249 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
f24b0feeed renamed ahbmulticontroller to ebu. 2022-09-26 14:37:18 -05:00
Ross Thompson
fd2a8e621a Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00
Ross Thompson
dcc00ef4b3 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
6a1b909a3f Fixed up IFU ahb interface names and widths. 2022-09-19 10:54:22 -05:00