cturek
9c70ab917c
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
Ross Thompson
a27b81ef90
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
3ac6514856
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
0ce3cc393a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-13 04:23:26 -08:00
David Harris
157f816cd3
HPTW cleanup
2022-11-13 04:23:23 -08:00
David Harris
0502b8ea4d
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
b812549f38
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
90697ef888
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
cturek
ff410cd849
Added integer step counter to fsm
2022-11-11 00:23:25 +00:00
Ross Thompson
c2e3bad3f5
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
7311eca5ff
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
64b818c49a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
31d5eabd77
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
3653d6b3ed
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
Ross Thompson
ebfee753ca
Updates to fpga constraints.
2022-11-09 13:52:36 -06:00
cturek
d5c5450f8d
Reoredered tests for arch32m
2022-11-09 18:42:00 +00:00
cturek
e7c25f9562
Fixed asign and bsign
2022-11-09 18:41:26 +00:00
Ross Thompson
42c0a10d07
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
9b20bf341e
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
fd1ef82310
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
Ross Thompson
922513c22f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-07 09:10:51 -06:00
Kip Macsai-Goren
6fdd603ba1
added potential fix to overrun error and fifo interrupt error. test passes
2022-11-06 22:01:02 -08:00
cturek
b137a95a35
propagated otfc swap to Rad2 and 4 qslc
2022-11-06 23:32:38 +00:00
Ross Thompson
8d57e488c8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-06 17:22:25 -06:00
cturek
1e927df1a0
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
56b7bb3590
Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv
2022-11-06 22:40:21 +00:00
cturek
ee048325cb
Added n and rightshiftx
2022-11-06 22:31:48 +00:00
cturek
67f2cb0595
p calculation
2022-11-06 22:24:21 +00:00
cturek
7567f388c2
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
333da5c945
Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
2022-11-06 22:08:18 +00:00
cturek
b893d9249d
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
Kip Macsai-Goren
b42fc7ec6d
fixed fifo timout handling. error now in data ready interrupt
2022-11-05 13:34:24 -07:00
David Harris
c78643f4e4
Reorder embench tests to prevent crash
2022-11-04 15:21:51 -07:00
David Harris
e57083a0ef
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
977ad1c33c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-04 13:30:08 -05:00
Kip Macsai-Goren
23268d22e5
fixed broken instructions so make works.
2022-11-03 23:06:20 +00:00
Ross Thompson
24689d6937
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-03 17:48:35 -05:00
Ross Thompson
24cb36c38d
Updated to put dtb into the rodata segment for our linker script.
2022-11-03 17:48:20 -05:00
cturek
39bf6a456e
renamed remOp to RemOp
2022-11-03 22:37:25 +00:00
Ross Thompson
041ab8e401
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-03 17:36:04 -05:00
Ross Thompson
34cfc01d1c
Potentially a valid zero stage boot loader based on cva6.
2022-11-03 17:35:57 -05:00
cturek
890b26466f
Added rem/div operation to postprocessor
2022-11-02 17:49:40 +00:00
Ross Thompson
98d4929c57
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
cturek
2a45787b37
Added buffered signals for int/fp
2022-10-28 21:47:24 +00:00
Ross Thompson
f81d1e15b6
More outline for uart timeout interrupt.
2022-10-28 13:53:56 -05:00
Ross Thompson
372b9890ef
Untested change to uart test for outline of how to handle rx fifo timeout.
2022-10-28 13:31:16 -05:00
cturek
2ae0a9bb5d
Config Cleanup
2022-10-27 22:38:56 +00:00
Ross Thompson
03f68a4cf5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-26 14:48:50 -05:00
Ross Thompson
36d9a00471
Fixed the uart transmit fifo overrun bug.
2022-10-26 14:48:09 -05:00
cturek
51fc4de0e1
small signal cleanup
2022-10-26 18:42:49 +00:00
